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| micron strataflash embedded memory p/n C pc28f128g18xx p/n C pc28f256g18xx p/n C pc28f512g18xx p/n C pc28f00ag18xx features ? high-performance read, program and erase C 96 ns initial read access C 108 mhz with zero wait-state synchronous burst reads: 7 ns clock-to-data output C 133 mhz with zero wait-state synchronous burst reads: 5.5 ns clock-to-data output C 8-, 16-, and continuous-word synchronous-burst reads C programmable wait configuration C customer-configurable output driver impedance C buffered programming: 2.0 s/word (typ), 512- mbit 65 nm C block erase: 0.9 s per block (typ) C 20 s (typ) program/erase suspend ? architecture C 16-bit wide data bus C multi-level cell technology C symmetrically-blocked array architecture C 256-kbyte erase blocks C 1-gbit device: eight 128-mbit partitions C 512-mbit device: eight 64-mbit partitions C 256-mbit device: eight 32-mbit partitions C 128-mbit device: eight 16-mbit partitions C read-while-program and read-while-erase C status register for partition/device status C blank check feature ? quality and reliability C expanded temperature: C30 c to +85 c C minimum 100,000 erase cycles per block C 65nm process technology ? power C core voltage: 1.7 v - 2.0 v C i/o voltage: 1.7 v - 2.0 v C standby current: 60 a (typ) for 512-mbit, 65 nm C deep power-down mode: 2 a (typ) C automatic power savings mode C 16-word synchronous-burst read current: 23 ma (typ) @ 108 mhz; 24 ma (typ) @ 133 mhz ? software C micron ? flash data integrator (fdi) optimized C basic command set (bcs) and extended com- mand set (ecs) compatible C common flash interface (cfi) capable ? security C one-time programmable (otp) space 64 unique factory device identifier bits 2112 user-programmable otp bits C absolute write protection: v pp = gnd C power-transition erase/program lockout C individual zero latency block locking C individual block lock-down ? density and packaging C 128mb, 256mb, 512mbit, and 1-gbit C address-data multiplexed and non-multiplexed interfaces C 64-ball easy bga 128mb, 256mb, 512mb, 1gb strataflash memory features pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 1 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. products and specifications discussed herein are subject to change by micron without notice.
contents general description ......................................................................................................................................... 8 functional overview ........................................................................................................................................ 8 configuration and memory map ....................................................................................................................... 9 device id ....................................................................................................................................................... 12 package dimensions ....................................................................................................................................... 13 signal assignments ......................................................................................................................................... 14 signal descriptions ......................................................................................................................................... 15 bus interface .................................................................................................................................................. 17 reset .......................................................................................................................................................... 17 standby ..................................................................................................................................................... 17 output disable ........................................................................................................................................... 17 asynchronous read .................................................................................................................................... 18 synchronous read ...................................................................................................................................... 18 burst wrapping .......................................................................................................................................... 18 end-of-wordline delay ............................................................................................................................... 19 write .......................................................................................................................................................... 20 command definitions .................................................................................................................................... 21 status register ................................................................................................................................................ 24 clear status register ................................................................................................................................... 25 read configuration register ........................................................................................................................... 26 programming the read configuration register ............................................................................................ 27 extended configuration register ..................................................................................................................... 28 output driver control ................................................................................................................................ 28 programming the extended configuration register ...................................................................................... 29 read operations ............................................................................................................................................. 30 read array ................................................................................................................................................. 30 read id ...................................................................................................................................................... 30 read cfi .................................................................................................................................................... 31 read status register ................................................................................................................................... 31 wait operation ......................................................................................................................................... 32 programming modes ...................................................................................................................................... 33 control mode ............................................................................................................................................. 33 object mode .............................................................................................................................................. 34 program operations ....................................................................................................................................... 38 single-word programming .......................................................................................................................... 38 buffered programming ............................................................................................................................... 39 buffered enhanced factory programming ................................................................................................... 39 erase operations ............................................................................................................................................ 42 block erase ............................................................................................................................................ 42 suspend and resume operations ................................................................................................................ 43 suspend operation .................................................................................................................................. 43 resume operation .................................................................................................................................... 44 blank check operation .............................................................................................................................. 45 block lock ..................................................................................................................................................... 46 one-time programmable operations .............................................................................................................. 48 programming otp area .............................................................................................................................. 50 reading otp area ....................................................................................................................................... 50 global main-array protection ......................................................................................................................... 51 dual operation .............................................................................................................................................. 52 power and reset specifications ....................................................................................................................... 53 128mb, 256mb, 512mb, 1gb strataflash memory features pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 2 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. initialization .............................................................................................................................................. 53 power-up and down .................................................................................................................................. 53 reset .......................................................................................................................................................... 53 automatic power saving ............................................................................................................................. 55 power supply decoupling ........................................................................................................................... 55 electrical specifications .................................................................................................................................. 56 electrical specifications C dc current and voltage characteristics and operating conditions ............................ 57 electrical specifications C ac characteristics and operating conditions ........................................................... 61 ac test conditions ..................................................................................................................................... 61 ac read specifications ................................................................................................................................... 63 ac read specifications (clk-latching, 133 mhz) ........................................................................................ 63 ac read timing .......................................................................................................................................... 64 ac write specifications ................................................................................................................................... 73 electrical specifications C program/erase characteristics ................................................................................. 80 common flash interface ................................................................................................................................ 81 read cfi structure output ........................................................................................................................ 81 cfi id string .............................................................................................................................................. 82 system interface information ...................................................................................................................... 82 device geometry definition ....................................................................................................................... 83 primary micron-specific extended query .................................................................................................... 86 flowcharts ..................................................................................................................................................... 92 aadm mode ................................................................................................................................................. 109 aadm feature overview ............................................................................................................................ 109 aadm mode enable (rcr[4] = 1) ............................................................................................................... 109 bus cycles and address capture ................................................................................................................. 109 wait behavior .......................................................................................................................................... 109 asynchronous read and write cycles ..................................................................................................... 110 asynchronous read cycles ....................................................................................................................... 110 asynchronous write cycles ..................................................................................................................... 112 synchronous read and write cycles ....................................................................................................... 113 synchronous read cycles ......................................................................................................................... 113 synchronous write cycles ....................................................................................................................... 116 system boot .............................................................................................................................................. 116 ordering information .................................................................................................................................... 117 revision history ............................................................................................................................................ 118 rev. f C 8/11 .............................................................................................................................................. 118 rev. e C 8/11 .............................................................................................................................................. 118 rev. d C 5/11 ............................................................................................................................................. 118 rev. c C 2/11 .............................................................................................................................................. 118 rev. b C 12/10 ............................................................................................................................................ 118 rev. a C 12/10 ............................................................................................................................................ 118 128mb, 256mb, 512mb, 1gb strataflash memory features pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 3 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. list of figures figure 1: 64-ball easy bga (8mm x 10mm x 1.2mm) ....................................................................................... 13 figure 2: 64-ball easy bga (top view, balls down) ......................................................................................... 14 figure 3: main array word lines .................................................................................................................... 19 figure 4: wrap/no-wrap example ................................................................................................................. 19 figure 5: end-of-wordline delay .................................................................................................................... 19 figure 6: two-cycle command sequence ....................................................................................................... 21 figure 7: single-cycle command sequence .................................................................................................... 21 figure 8: read cycle between write cycles ................................................................................................. 21 figure 9: illegal command sequence ............................................................................................................. 22 figure 10: configurable programming regions: control mode and object mode .............................................. 34 figure 11: configurable programming regions: control mode and object mode segments .............................. 36 figure 12: block lock operations ............................................................................................................... 47 figure 13: otp area map ............................................................................................................................... 49 figure 14: v pp supply connection example .................................................................................................... 51 figure 15: reset operation waveforms ......................................................................................................... 54 figure 16: ac input/output reference waveform ........................................................................................... 61 figure 17: transient equivalent testing load circuit ....................................................................................... 61 figure 18: clock input ac waveform .............................................................................................................. 62 figure 19: asynchronous page-mode read (non-mux) .................................................................................. 65 figure 20: synchronous 8- or 16-word burst read (non-mux) ........................................................................ 66 figure 21: synchronous continuous misaligned burst read (non-mux) ......................................................... 67 figure 22: synchronous burst with burst interrupt read (non-mux) .............................................................. 68 figure 23: asynchronous single-word read .................................................................................................... 69 figure 24: synchronous 8- or 16-word burst read (a/d mux) ......................................................................... 70 figure 25: synchronous continuous misaligned burst read (a/d mux) .......................................................... 71 figure 26: synchronous burst with burst-interrupt (ad-mux) ......................................................................... 71 figure 27: write timing ................................................................................................................................. 74 figure 28: write to write (non-mux) .............................................................................................................. 75 figure 29: async read to write (non-mux) ..................................................................................................... 75 figure 30: write to async read (non-mux) ..................................................................................................... 76 figure 31: sync read to write (non-mux) ....................................................................................................... 76 figure 32: write to sync read (non-mux) ....................................................................................................... 77 figure 33: write to write (ad-mux) ................................................................................................................ 77 figure 34: async read to write (ad-mux) ....................................................................................................... 78 figure 35: write to async read (ad-mux) ....................................................................................................... 78 figure 36: sync read to write (ad-mux) ......................................................................................................... 79 figure 37: write to sync read (ad-mux) ......................................................................................................... 79 figure 38: word program procedure ............................................................................................................... 92 figure 39: word program full status check procedure .................................................................................... 93 figure 40: program suspend/resume procedure ............................................................................................ 94 figure 41: buffer programming procedure ...................................................................................................... 96 figure 42: buffered enhanced factory programming (befp) procedure ........................................................... 98 figure 43: block erase procedure .................................................................................................................. 100 figure 44: block erase full status check procedure ........................................................................................ 101 figure 45: erase suspend/resume procedure ................................................................................................ 102 figure 46: block lock operations procedure .................................................................................................. 104 figure 47: protection register programming procedure ................................................................................. 105 figure 48: protection register programming full status check procedure ....................................................... 106 figure 49: blank check procedure ................................................................................................................. 107 figure 50: blank check full status check procedure ...................................................................................... 108 128mb, 256mb, 512mb, 1gb strataflash memory features pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 4 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 51: aadm asynchronous read cycle (latching a[max:0]) ................................................................. 111 figure 52: aadm asynchronous read cycle (latching a[15:0] only) .............................................................. 111 figure 53: aadm asynchronous write cycle (latching a[max:0]) ................................................................ 112 figure 54: aadm asynchronous write cycle (latching a[15:0] only) ............................................................ 113 figure 55: aadm synchronous burst read cycle (adv# de-asserted between address cycles) ....................... 114 figure 56: aadm synchronous burst read cycle (adv# not de-asserted between address cycles) ................ 115 figure 57: aadm synchronous burst read cycle (latching a[15:0] only) ....................................................... 115 figure 58: part number chart for g18 components ....................................................................................... 117 128mb, 256mb, 512mb, 1gb strataflash memory features pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 5 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. list of tables table 1: main array memory map C 128mb, 256mb ........................................................................................... 9 table 2: main array memory map C 512mb, 1gb ............................................................................................. 10 table 3: device id codes ............................................................................................................................... 12 table 4: signal descriptions ........................................................................................................................... 15 table 5: address mapping for address/data mux mode .................................................................................. 16 table 6: bus control signals ........................................................................................................................... 17 table 7: command set .................................................................................................................................. 22 table 8: status register bit definitions (default value = 0080h) ....................................................................... 24 table 9: clear status register command bus cycles ............................................................................... 25 table 10: read configuration register bit definitions ..................................................................................... 26 table 11: supported clock frequencies .......................................................................................................... 26 table 12: program read configuration register bus cycles .............................................................. 27 table 13: extended configuration register bit definitions (default value = 0004h) ........................................... 28 table 14: output driver control characteristics .............................................................................................. 28 table 15: program extended configuration register command bus cycles ...................................................... 29 table 16: read mode command bus cycles ................................................................................................. 30 table 17: device information ......................................................................................................................... 31 table 18: wait behavior summary C non-mux ............................................................................................. 32 table 19: wait behavior summary C ad mux ................................................................................................ 32 table 20: programming region next state ...................................................................................................... 37 table 21: program command bus cycles .................................................................................................... 38 table 22: befp requirements and considerations .......................................................................................... 40 table 23: erase command bus cycle ............................................................................................................ 42 table 24: valid commands during suspend ................................................................................................... 43 table 25: suspend and resume command bus cycles ................................................................................ 44 table 26: blank check command bus cycles ............................................................................................. 45 table 27: block lock command bus cycles ................................................................................................ 46 table 28: block lock configuration ................................................................................................................ 47 table 29: program otp area command bus cycles ......................................................................................... 48 table 30: dual operation restrictions ............................................................................................................ 52 table 31: power sequencing ........................................................................................................................... 53 table 32: reset specifications ........................................................................................................................ 54 table 33: absolute maximum ratings ............................................................................................................. 56 table 34: operating conditions ...................................................................................................................... 56 table 35: dc current characteristics and operating conditions ...................................................................... 57 table 36: dc voltage characteristics and operating conditions ...................................................................... 60 table 37: ac input requirements ................................................................................................................... 61 table 38: test configuration load capacitor values for worst case speed conditions ...................................... 61 table 39: capacitance .................................................................................................................................... 62 table 40: ac read specifications (clk-latching, 133 mhz), v ccq = 1.7v to 2.0v ............................................... 63 table 41: ac write specifications ................................................................................................................... 73 table 42: program/erase characteristics ........................................................................................................ 80 table 43: example of cfi output (x16 device) as a function of device and mode ............................................. 81 table 44: cfi database: addresses and sections ............................................................................................. 81 table 45: cfi id string ................................................................................................................................... 82 table 46: system interface information .......................................................................................................... 82 table 47: device geometry ............................................................................................................................ 83 table 48: block region map information ........................................................................................................ 84 table 49: primary micron-specific extended query ........................................................................................ 86 table 50: one time programmable (otp) space information .......................................................................... 87 128mb, 256mb, 512mb, 1gb strataflash memory features pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 6 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. table 51: burst read informaton .................................................................................................................... 88 table 52: partition and block erase region information .................................................................................. 89 table 53: partition region 1 information: top and bottom offset/address ....................................................... 89 table 54: partition and erase block map information ...................................................................................... 91 table 55: aadm asynchronous and latching timings ................................................................................... 110 table 56: aadm asynchronous write timings ............................................................................................... 112 table 57: aadm synchronous timings .......................................................................................................... 113 table 58: valid line items ............................................................................................................................. 117 128mb, 256mb, 512mb, 1gb strataflash memory features pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 7 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. general description micron's 65nm device is the latest generation of strataflash ? wireless memory featur- ing flexible, multiple-partition, dual-operation architecture. the device provides high- performance, asynchronous read mode and synchronous-burst read mode using 1.8v low-voltage, multilevel cell (mlc) technology. the multiple-partition architecture enables background programming or erasing to oc- cur in one partition while code execution or data reads take place in another partition. this dual-operation architecture also allows two processors to interleave code opera- tions while program and erase operations take place in the background. the multi- ple partitions allow flexibility for system designers to choose the size of the code and data segments. the device is manufactured using 65nm process technologies and is available in indus- try-standard chip scale packaging. functional overview this device provides high read and write performance at low voltage on a 16-bit data bus. the multi-partition architecture provides read-while-write and read-while-erase capability, with individually erasable memory blocks sized for optimum code and data storage. this device is offered in densities from 128mb to 1gb. the device supports synchronous burst reads up to 133 mhz using enhanced clk latching for all densities on 45nm. upon initial power-up or return from reset, the device defaults to asynchronous read mode. configuring the read configuration register enables synchronous burst mode reads. in synchronous burst mode, output data is synchronized with a user-supplied clock signal. in continuous-burst mode, a data read can traverse partition boundaries. a wait signal simplifies synchronizing the cpu to the memory. designed for low-voltage applications, the device supports read operations with v cc at 1.8v, and erase and program operations with v pp at 1.8v or 9.0v. v cc and v pp can be tied together for a simple, ultra low-power design. in addition to voltage flexibility, a dedicated v pp connection provides complete data protection when v pp is less than v pplk . a status register provides status and error conditions of erase and program opera- tions. one-time programmable (otp) area enables unique identification that can be used to increase security. additionally, the individual block lock feature provides zero-latency block locking and unlocking to protect against unwanted program or erase of the array. the device offers power-savings features, including automatic power savings mode, standby mode, and deep power-down mode. for power savings, the device automati- cally enters aps following a read cycle. standby is initiated when the system deselects the device by de-asserting ce#. deep power-down provides the lowest power consump- tion and is enabled by programming in the extended configuration register. dpd is ini- tiated by asserting the dpd pin. 128mb, 256mb, 512mb, 1gb strataflash memory general description pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 8 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. configuration and memory map the device features a symmetrical block architecture. the main array of the 128mb de- vice is divided into eight 16mb partitions. each partition is divided into eight 256kb blocks (8 x 8 = 64 blocks). the main array of the 256mb device is divided into eight 32mb partitions. each parti- tion is divided into sixteen 256kb blocks (8 x 16 = 128 blocks). the main array of the 512mb device is divided into eight 64mb partitions. each parti- tion is divided into thirty-two 256kb blocks (8 x 32 = 256 blocks). the main array of the 1gb device is divided into eight 128mb partitions. each partition is divided into sixty-four 256kb blocks (8 x 64 = 512 blocks). each block is divided into as many as 256 1kb programming regions. each region is divided into as many as thirty-two 32-byte segments table 1: main array memory map C 128mb, 256mb 128mb 256mb partition size (mb) block # address range size (mb) block # address range 7 16 63 07e0000-07fffff 32 127 ff0000-ffffff . . . . . . . . . . . . 56 0700000-071ffff 112 fd0000-fdffff 6 16 55 06e0000-06fffff 32 111 0de0000-0dfffff . . . . . . . . . . . . 48 0600000-061ffff 96 0c00000-0c1ffff 5 16 47 05e0000-05fffff 32 95 0be0000-0bfffff . . . . . . . . . . . . 40 0500000-051ffff 80 0a00000-0a1ffff 4 16 39 04e0000-04fffff 32 79 09e0000-09fffff . . . . . . . . . . . . 32 0400000-041ffff 64 0800000-081ffff 3 16 31 03e0000-03fffff 32 63 07e0000-07fffff . . . . . . . . . . . . 24 0300000-031ffff 48 0600000-061ffff 128mb, 256mb, 512mb, 1gb strataflash memory configuration and memory map pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 9 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. table 1: main array memory map C 128mb, 256mb (continued) 128mb 256mb partition size (mb) block # address range size (mb) block # address range 2 16 23 02e0000-02fffff 32 47 05e0000-05fffff . . . . . . . . . . . . 16 0200000-021ffff 32 0400000-041ffff 1 16 15 01e0000-01fffff 32 31 03e0000-03fffff . . . . . . . . . . . . 8 0100000-011ffff 16 0200000-021ffff 0 16 7 00e0000-00fffff 32 15 01e0000-01fffff . . . . . . . . . . . . 0 0000000-001ffff 0 0000000-001ffff table 2: main array memory map C 512mb, 1gb 512mb 1gb partition size (mb) block # address range size (mb) block # address range 7 64 255 1fe0000-1ffffff 128 511 3fe0000-3ffffff . . . . . . . . . . . . 224 1c00000-1c1ffff 448 3800000-381ffff 6 64 223 1be0000-1bfffff 128 447 37e0000-37fffff . . . . . . . . . . . . 192 1800000-181ffff 384 3000000-301ffff 5 64 191 17e0000-17fffff 128 383 2fe0000-2ffffff . . . . . . . . . . . . 160 1400000-141ffff 320 2800000-281ffff 128mb, 256mb, 512mb, 1gb strataflash memory configuration and memory map pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 10 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. table 2: main array memory map C 512mb, 1gb (continued) 512mb 1gb partition size (mb) block # address range size (mb) block # address range 4 64 159 13e0000-13fffff 128 319 27e0000-27fffff . . . . . . . . . . . . 128 1000000-101ffff 256 2000000-201ffff 3 64 127 0fe0000-0ffffff 128 255 1fe0000-1ffffff . . . . . . . . . . . . 96 0300000-031ffff 192 1800000-181ffff 2 64 95 0be0000-0bfffff 128 191 17e0000-17fffff . . . . . . . . . . . . 64 0800000-081ffff 128 1000000-101ffff 1 64 63 07e0000-07fffff 128 127 0fe0000-0ffffff . . . . . . . . . . . . 32 0400000-041ffff 64 0800000-081ffff 0 64 31 03e0000-03fffff 128 63 07e0000-07fffff . . . . . . . . . . . . 0 0000000-001ffff 0 0000000-001ffff 128mb, 256mb, 512mb, 1gb strataflash memory configuration and memory map pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 11 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. device id to order parts or to obtain a data sheet, contact the factory. table 3: device id codes density product device identifier code (hex) 128mb non-mux a/d mux 8900 8903 256mb non-mux a/d mux 8901 8904 512mb non-mux a/d mux 887e 8881 1024mb non-mux a/d mux 88b0 88b1 128mb, 256mb, 512mb, 1gb strataflash memory device id pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 12 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. package dimensions figure 1: 64-ball easy bga (8mm x 10mm x 1.2mm) ball a1 id 0.78 typ seating plane 0.1 1.20 max 1.00 typ a b c d e f g h 8 7 6 5 4 3 2 1 0.5 0.1 10 0.1 64x ?0.43 0.1 1.00 typ 8 0.1 1.5 0.1 ball a1 id note: 1. all dimensions are in millimeters. 128mb, 256mb, 512mb, 1gb strataflash memory package dimensions pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 13 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. signal assignments figure 2: 64-ball easy bga (top view, balls down) a b c d e f g h 1 a1 a2 a3 a4 dq8 rfu a23 rfu 2 a6 v ss a7 a5 dq1 dq0 rfu v ssq 3 a8 a9 a10 a11 dq9 dq10 dq2 v cc 4 v pp ce# a12 rst# dq3 dq11 v ccq v ss 5 a13 a14 a15 v ccq dq4 dq12 dq5 dq13 6 v cc a25 wp# v ccq clk adv# dq6 v ssq 7 a18 a19 a20 a16 dq15 wait dq14 dq7 8 a22 a26 a21 a17 rfu oe# we# a24 notes: 1. a1 is the least significant address bit. 2. b6 is a25 for 512mb densities and above; otherwise, it is a no connect (nc). 3. b8 is a26 for 1gb density; otherwise, it is a no connect (nc). 4. g1 is a23 for 128mb density and above; otherwise, it is a no connect (nc). 5. h8 is a24 for 256mb density and above; otherwise, it is a no connect (nc). 128mb, 256mb, 512mb, 1gb strataflash memory signal assignments pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 14 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. signal descriptions table 4: signal descriptions symbol type description non-mux a[max:1] input address inputs: address inputs for all read/write cycles. dq[15:0] input/output data: data or command inputs during write cycles; data, status, or device informa- tion outputs during read cycles. a/d mux a[max:17] input address inputs: upper address inputs for all read/write cycles. adq[15:0] input/output address or data: lower address inputs during the address phase for all read/write cycles; data or command inputs during write cycles; data, status, or device informa- tion outputs during read cycles. control signals ce# input chip enable: low true input. when low, ce# selects the die; when high, ce# dese- lects the die and places it in standby. oe# input output enable: low true input. must be low for reads and high for writes. we# input write enable: low true input. must be low for writes and high for reads. clk input clock: synchronizes burst read operations with the host controller. adv# input address valid: low true input. when low, adv# enables address inputs. for syn- chronous burst reads, address inputs are latched on the rising edge. wp# input write protect: low true input. when low, wp# enables block lock down; when high, wp# disables block lock down. rst# input reset: low true input. when low, rst# inhibits all operations; must be high for normal operations. v pp input erase/program voltage: enables voltage for program and erase operations. array contents cannot be altered when v pp is at or below v pplk . wait output wait: configurable high or low true output. when asserted, wait indicates dq[15:0] is invalid; when de-asserted, wait indicates dq[15:0] is valid. v cc power core power: supply voltage for core circuits. all operations are inhibited when v cc is at or below v lko . v ccq power i/o power: supply voltage for all i/o drivers. all operations are inhibited when v ccq is at or below v lkoq . v ss power logic ground: core logic ground return. connect all v ss balls to system ground; do not float any v ss balls. v ssq power i/o ground: i/o driver ground return. connect all v ssq balls to system ground; do not float any v ssq balls. 128mb, 256mb, 512mb, 1gb strataflash memory signal descriptions pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 15 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. table 5: address mapping for address/data mux mode address a/d mux configuration aadm mode (rcr bit 4 = 1) and oe# = 1 aadm mode (rcr bit 4 = 1) and oe# = 0 a1 dq0 a1 a17 a2 dq1 a2 a18 a3 dq2 a3 a19 a4 dq3 a4 a20 a5 dq4 a5 a21 a6 dq5 a6 a22 a7 dq6 a7 a23 a8 dq7 a8 a24 a9 dq8 a9 a25 a10 dq9 a10 a26 a11 dq10 a11 C a12 dq11 a12 C a13 dq12 a13 C a14 dq13 a14 C a15 dq14 a15 C a16 dq15 a16 C a17 a17 gnd gnd a18 a18 gnd gnd a19 a19 gnd gnd a20 a20 gnd gnd a21 a21 gnd gnd a22 a22 gnd gnd a23 a23 gnd gnd a24 a24 gnd gnd a25 a25 gnd gnd a26 a26 gnd gnd 128mb, 256mb, 512mb, 1gb strataflash memory signal descriptions pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 16 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. bus interface the bus interface uses cmos-compatible address, data, and bus control signals for all bus write and bus read operations. the address signals are input only, the data sig- nals are input/output (i/o), and the bus control signals are input only. the address in- puts are used to specify the internal device location during bus read and bus write operations. the data i/os carry commands, data, or status to and from the device. the control signals are used to select and deselect the device, indicate a bus read or bus write operation, synchronize operations, and reset the device. do not float any inputs. all inputs must be driven or terminated for proper device oper- ation. some features may use additional signals. see signal descriptions for descrip- tions of these signals. the following table shows the logic levels that must be applied to the bus control signal inputs for the bus operations listed. table 6: bus control signals x = dont care; high = v ih ; low = v il bus operations rst# ce# clk adv# oe# we# address data i/o reset low x x x x x x high-z standby high high x x x x x high-z output disable high x x x high x x high-z asynchronous read high low x low low high valid output synchronous read high low running toggle low high valid output write high low x x high low valid input reset rst# low places the device in reset, where device operations are disabled; inputs are ignored, and outputs are placed in high-z. any ongoing erase or program operation will be aborted and data at that location will be indeterminate. rst# high enables normal device operations. a minimum delay is required before the device is able to perform a bus read or bus write operation. see ac specifications. standby rst# high and ce# high place the device in standby, where all other inputs are ignor- ed, outputs are placed in high-z (independent of the level placed on oe#), and power consumption is substantially reduced. any ongoing erase or program operation continues in the background and the de- vice draws active current until the operation has finished. output disable when oe# is deasserted with ce# asserted, the device outputs are disabled. output pins are placed in a high-impedance state. wait is deasserted in ad-muxed devices and driven to high-z in non-multiplexed devices. 128mb, 256mb, 512mb, 1gb strataflash memory bus interface pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 17 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. asynchronous read for rcr15 = 1 (default), ce# low and oe# low place the device in asynchronous bus read mode: ? rst# and we# must be held high; clk must be tied either high or low. ? address inputs must be held stable throughout the access, or latched with adv#. ? adv# must be held low or can be toggled to latch the address. ? valid data is output on the data i/os after t avqv, t elqv, t vlqv, or t glqv, whichever is satisfied last. asynchronous read operations are independent of the voltage level on v pp . for asynchronous page reads, subsequent data words are output t apa after the least sig- nificant address bit(s) are toggled: 16-word page buffer, a[3:0]. synchronous read for rcr15 = 0, ce# low, oe# low, and adv# low place the device in synchronous bus read mode: ? rst# and we# must be held high. ? clk must be running. ? the first data word is output t chqv after the latency count has been satisfied. ? for array reads, the next address data is output t chqv after valid clk edges until the burst length is satisfied. ? for nonarray reads, the same address data is output t chqv after valid clk edges until the burst length is satisfied. the address for synchronous read operations is latched on the adv# rising edge or the first rising clk edge after adv# low, whichever occurs first for devices that support up to 108 mhz. for devices that support up to 133 mhz, the address is latched on the last clk edge when adv# is low. burst wrapping data stored within the memory array is arranged in rows or word lines. during synchro- nous burst reads, data words are sensed in groups from the array. the starting address of a synchronous burst read determines which word within the wordgroup is output first, and subsequent words are output in sequence until the burst length is satisfied. the setting of the burst wrap bit (rcr3) determines whether synchronous burst reads will wrap within the wordgroup or continue on to the next wordgroup. 128mb, 256mb, 512mb, 1gb strataflash memory bus interface pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 18 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 3: main array word lines 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 1 2 3 4 5 6 7 8 9 a b c d e f 256 bits 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 1 2 3 4 5 6 7 8 9 a b c d e f 16-bit data word 0x000000 0x000010 0x000020 0x000030 bit lines word lines 16-word sense group address figure 4: wrap/no-wrap example 2 3 4 5 6 7 8 9 a b 2 3 4 5 6 7 8 9 a b 16-bit data word no wrap wrap end-of-wordline delay output delays may occur when the burst sequence crosses the first end-of-wordline boundary onto the start of the next wordline. no delays occur if the starting address is sense-group aligned or if the burst sequence never crosses a wordline boundary. however, if the starting address is not sense-group aligned, the worst-case end-of-wordline delay is one clock cycle less than the initial ac- cess latency count used. this delay occurs only once during the burst access. wait in- forms the system of this delay when it occurs. figure 5: end-of-wordline delay 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 1 2 3 4 5 6 7 8 9 a b c d e f 0x000010 0x000020 eowl delay 128mb, 256mb, 512mb, 1gb strataflash memory bus interface pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 19 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. write ce# low and we# low place the device in bus write mode, where rst# and oe# must be high, clk and adv# are ignored, input data and address are sampled on the rising edge of we# or ce#, whichever occurs first. during a write operation in muxed devices, address is latched during the rising edge of adv# or ce# whichever occurs first and data is latched during the rising edge of we# or ce# whichever occurs first. bus write cycles are asynchronous only. the following conditions apply when a bus write cycle occurs immediately before, or immediately after, a bus read cycle: ? when transitioning from a bus read cycle to a bus write cycle, ce# or adv# must toggle after oe# goes high. ? when in synchronous read mode (rcr15 = 0; burst clock running), bus write cycle timings t vhwl (adv# high to we# low), t chwl (clk high to we# low), and t whch (we# high to clk high) must be met. ? when transitioning from a bus write cycle to a bus read cycle, ce# or adv# must toggle after we# goes high. 128mb, 256mb, 512mb, 1gb strataflash memory bus interface pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 20 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. command definitions commands are written to the device to control all operations. some commands are two-cycle commands that use a setup and a confirm command; other commands are single-cycle commands that use only a setup command followed by a data read cycle or data write cycle. valid commands and their associated command codes are shown in the table below. the device supports read-while-write and read-while-erase operations with bus cycle granularity, not command granularity. that is, both bus write cycles of a two-cy- cle command do not need to occur as back-to-back bus write cycles to the device; read cycles may occur between the two write write cycles of a two-cycle command. however, a write operation must not occur between the two bus write cycles of a two-cycle command; this will cause a command sequence error (sr[7,5,4] = 1). due to the large buffer size of devices, the system interrupt latency may be impacted during the buffer fill phase of a buffered programming operation. please refer to the rel- evant application note to implement a software solution for your system figure 6: two-cycle command sequence partition a partition a partition b setup confirm 00ffh address we# oe# d/q figure 7: single-cycle command sequence partition a partition a partition b setup 00ffh address we# oe# d/q figure 8: read cycle between write cycles partition a partition b partition a setup confirm address we# oe# d/q read data 128mb, 256mb, 512mb, 1gb strataflash memory command definitions pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 21 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 9: illegal command sequence partition a partition a partition a partition b setup confirm address we# oe# d/q write data status table 7: command set command code (setup/confirm) description register operations program read configura- tion register 0060h/0003h programs the read configuration register. the desired read con- figuration register value is placed on the address bus, and writ- ten to the read configuration register when the confirm com- mand is issued. program extended configu- ration register 0060h/0004h programs the extended configuration register. the desired ex- tended configuration register value is placed on the address bus, and written to the read configuration register when the con- firm command is issued. program otp area 00c0h programs otp area and otp lock registers. the desired register data is written to the addressed register on the next write cy- cle. clear status register 0050h clears all error bits in the status register. read mode operations read array 00ffh places the addressed partition in read array mode. subsequent reads outputs array data. read status register 0070h places the addressed partition in read status mode. subsequent reads outputs status register data. read id 0090h places the addressed partition in read id mode. subsequent reads from specified address offsets output unique device infor- mation. read cfi 0098h places the addressed partition in read cfi mode. subsequent reads from specified address offsets output cfi data. array programming operations single-word program 0041h programs a single word into the array. data is written to the ar- ray on the next write cycle. the addressed partition automati- cally switches to read status register mode. buffered program 00e9h/00d0h initiates and executes a buffered program operation. addi- tional bus read/write cycles are required between the and confirm commands to properly perform this operation. the ad- dressed partition automatically switches to read status register mode. 128mb, 256mb, 512mb, 1gb strataflash memory command definitions pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 22 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. table 7: command set (continued) command code (setup/confirm) description buffered enhanced factory program 0080h/00d0h initiates and executes a buffered enhanced factory pro- gram operation. additional bus read/write cycles are re- quired after the confirm command to properly perform this operation. the addressed partition automatically switches to read status register mode. block erase operations block erase 0020h/00d0h erases a single, addressed block. the erase operation commen- ces when the confirm command is issued. the addressed parti- tion automatically switches to read status register mode. security operations lock block 0060h/0001h sets the lock bit of the addressed block. unlock block 0060h/00d0h clears the lock bit of the addressed block. lock-down block 0060h/002fh sets the lock-down bit of the addressed block. other operations suspend 00b0h initiates a suspend of a program or block erase operation already in progress when issued to any device address sr[6] = 1 indicates erase suspend sr[2] = 1 indicates program suspend resume 00d0h resumes a suspended program or block erase operation when issued to any device address. a program suspend nested within an erase suspend is resumed first. blank check 00bch/00d0h performs a blank check of an addressed block. the addressed partition automatically switches to read status register mode. 128mb, 256mb, 512mb, 1gb strataflash memory command definitions pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 23 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. status register the status register is a 16-bit, read-only register that indicates device status, region sta- tus, and operating errors. upon power-up or exit from reset, the status register defaults to 0080h (device ready, no errors). the status register has status bits and error bits. status bits are set and cleared by the device; error bits are only set by the device. error bits are cleared using the clear sta- tus register command or by resetting the device. to read from the status register, first issue the read status register command and then read from the device. note that some commands automatically switch from read mode to read status register mode. table 8: status register bit definitions (default value = 0080h) bit name description 15:10 reserved reserved for future use; these bits will always be set to zero 9:8 partition program er- ror sr[9]/sr[8] 0 0 = region program successful 1 0 = region program error: attempted write with object data to control mode region 0 1= region-program error: attempted rewrite to object mode region 1 1 = region-program error: attempted write using illegal command (sr[4] will also be set along with sr[8,9] for the above error conditions 7 device status 0 = device is busy; sr[9,8,6:1] are invalid, sr[0] is valid 1 = device is ready; sr[9:8], sr[6:1] are valid 6 erase suspend 0 = erase suspend not in effect 1 = erase suspend in effect 5:4 erase error/blank check error program error (command sequence error) sr[5]/sr[4] 0 0 = program or erase operation successful 0 1 = program error: operation aborted 1 0 = erase error: operation aborted; blank check error: operation failed 1 1 = command sequence error: command aborted 3 v pp error 0 = v pp within acceptable limits during program or erase 1 = v pp < v pplk during program or erase; operation aborted 2 program suspend 0 = program suspend not in effect 1 = program suspend in effect 1 block lock error 0 = block not locked during program or erase; operation successful 1 = block locked during program or erase; operation aborted 0 partition status sr[7]/sr[0] 0 0 = active program or erase operation in addressed partition befp: program or verify complete, or ready for data 0 1 = active program or erase operation in other partition befp: program or verify in progress 1 0 = no active program or erase operation in any partition befp: operation complete 1 1 = reserved 128mb, 256mb, 512mb, 1gb strataflash memory status register pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 24 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. clear status register the status register has status bits and error bits. status bits are set and cleared by the device; error bits are only set by the device. error bits are cleared using the clear sta- tus register command or by resetting the device. note: care should be taken to avoid status register ambiguity. if a command sequence error occurs while in erase suspend, sr[5:4] will be set, indicating a command sequence error. when the erase operation is resumed (and finishes), any errors that may have occurred during the erase operation will be masked by the command sequence error. to avoid this situation, clear the status register prior to resuming any suspended erase operation. the clear status register command functions independent of the voltage level on v pp . issuing the clear status register command places the addressed partition in read status register mode. other partitions are not affected. table 9: clear status register command bus cycles command setup write cycle address bus setup write cycle data bus confirm write cycle address bus confirm write cycle data bus clear status register device address 0050h C C 128mb, 256mb, 512mb, 1gb strataflash memory status register pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 25 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. read configuration register the read configuration register is a volatile, 16-bit read/write register used to select bus read modes and to configure synchronous burst read behavior of the device. the read configuration register is programmed using the program read configu- ration register command. to read the read configuration register, issue the read id command and then read from offset 0005h. upon power-up or exit from reset, the read configuration register defaults to asynchro- nous mode (rcr15 = 1; all other bits are ignored). table 10: read configuration register bit definitions bit name description 15 read mode 0 = synchronous burst mode 1 = asynchronous mode (default) 14:11 latency count 0 0 1 1 = code 3 0 1 0 0 = code 4 0 1 0 1 = code 5 0 1 1 0 = code 6 0 1 1 1 = code 7 1 0 0 0 = code 8 1 0 0 1 = code 9 1 0 1 0 = code 10 1 0 1 1 = code 11 1 1 0 0 = code 12 1 1 0 1 = code 13 other bit settings are reserved; see the table below for supported clock frequencies 10 wait polarity 0 = wait signal is low-true 1 = wait signal is high-true 9 reserved write 0 to reserved bits 8 wait delay 0 = wait de-asserted with valid data 1 = wait de-asserted one clock cycle before valid data 7:3 reserved write 0 to reserved bits 2:0 burst length 0 1 0 = 8-word burst, wrap only 0 1 1 = 16-word burst, wrap only 1 1 1 = continuous-burst: linear, no-wrap only other bit settings are reserved table 11: supported clock frequencies latency count code clock frequency v ccq = 1.7v to 2.0v 3 32.6 mhz 4 43.5 mhz 5 54.3 mhz 6 65.2 mhz 128mb, 256mb, 512mb, 1gb strataflash memory read configuration register pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 26 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. table 11: supported clock frequencies (continued) latency count code clock frequency v ccq = 1.7v to 2.0v 7 76.1 mhz 8 87.0 mhz 9 97.8 mhz 10 108.7 mhz 11 119.6 mhz 12 130.4 mhz 13 133.3 mhz programming the read configuration register the read configuration register is programmed by issuing the program read con- figuration register command. the desired rcr[15:0] settings are placed on a[15:0], while the program read configuration register setup command is placed on the data bus. upon issuing the setup command, the read mode of the ad- dressed partition is automatically changed to read status register mode. next, the confirm command is placed on the data bus while the desired settings for rcr[15:0] are again placed on a[16:1]. upon issuing the confirm command, the read mode of the addressed partition is automatically switched to read array mode. because the desired read configuration register value is placed on the address bus, any hardware-connection offsets between the hosts address outputs and the devices ad- dress inputs must be taken into account. for example, if the hosts address outputs are aligned to the devices address inputs such that host address bit a1 is connected to ad- dress bit a0, the desired register value must be left-shifted by one (for example, 2532h << 4a64h) before programming the read configuration register synchronous read accesses cannot occur until both the device and the host are in syn- chronous read mode. therefore, the software instructions used to perform read config- uration register programming and host chip select configuration must be guaranteed not to fetch from the device (instructions must be in system ram or locked in cache). this also applies when switching back to asynchronous read mode from synchronous read mode. table 12: program read configuration register bus cycles command setup write cycle address bus setup write cycle data bus confirm write cycle address bus confirm write cycle data bus program read configuration register rcr settings 0060h rcr settings 0003h 128mb, 256mb, 512mb, 1gb strataflash memory read configuration register pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 27 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. extended configuration register the extended configuration register is a volatile 16-bit, read/write register used to select deep-power down and output-driver strength of the device. upon power-up or exit from reset, the extended configuration register defaults to 0004h. the extended configuration register is programmed using the program extended configuration register command. to read the extended configuration register, issue the read id command to a partition, and read from programming the extended configuration register the extended configuration register is programmed by issuing the program exten- ded configuration register command. the desired ecr[15:0] settings are placed on a[15:0], while the program extended configuration register set- up command is placed on the data bus. upon issuing the setup command, the read mode of the addressed partition is automatically changed to read status register mode. next, the confirm command is placed on the data bus while the desired settings for ecr[15:0] are again placed on a[15:0]. upon issuing the confirm command, the read mode of the addressed partition is automatically switched to read array mode. because the desired ecr value is placed on the address bus, any hardware-connection offsets between the hosts address outputs and the devices address inputs must be tak- en into account. for example, if the hosts address outputs are aligned to the devices address inputs such that host address bit a1 is connected to address bit a0, the desired register value must be left-shifted by one (for example, 2532h << 4a64h) before programming the ecr. programming the ecr functions independently of the voltage on v pp . table 15: program extended configuration register command bus cycles command setup write cycle address bus setup write cycle data bus confirm write cycle address bus confirm write cycle data bus program extended configuration register register data 0060h register data 0004h 128mb, 256mb, 512mb, 1gb strataflash memory extended configuration register pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 29 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. read operations the following types of data can be read from the device: array data (read array), device information (read id), cfi data (read cfi), and device status (read status register). upon power-up or return from reset, the device defaults to read array mode. to change the read mode, the appropriate command must be issued to the device. the table below shows the command codes used to configure the device for the desired read mode. table 16: read mode command bus cycles command setup write cycle address bus setup write cycle data bus confirm write cycle address bus confirm write cycle data bus read array partition address 00ffh C C read status regis- ter partition address 0070h C C read id partition address 0090h C C read cfi partition address 0098h C C read array upon power-up or exit from reset, the device defaults to read array mode. issuing the read array command places the addressed partition in read array mode and can only be issued to a partition that is not actively programming or erasing. subsequent reads output array data from that partition. the addressed partition remains in read array mode until a different read command is issued, a program or erase operation is performed, or a block lock setup com- mand is issued in that partition, in which case the read mode automatically changes to read status. to change a partition that is actively programming or erasing to read array mode, first issue the suspend command. after the operation has been suspended, issue the read array command to the partition. when the program or erase operation is subse- quently resumed, the partition will automatically revert back to read status mode. the read array command functions independently of the voltage level on v pp . issuing the read array command to a partition that is actively programming or eras- ing causes subsequent reads from that partition to output invalid data. valid array data is output only after the program or erase operation has completed. read id issuing the read id command places the addressed partition in read id mode. subse- quent reads output device information such as manufacturer code, device identifier code, block lock status, otp data, or read configuration register data. the addressed partition remains in read id mode until a different read command is issued, or a program or erase operation is performed in that partition, in which case the read mode automatically changes to read status. the read id command functions independently of the voltage level on v pp . 128mb, 256mb, 512mb, 1gb strataflash memory read operations pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 30 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. issuing the read id command to a partition that is actively programming or erasing changes that partitions read mode to read id mode. subsequent reads from that parti- tion will not output device information until the program or erase operation has completed. table 17: device information device information address bus data bus device manufacturer code partition base address + 00h 0089h device id code partition base address + 01h device id block lock status block base address + 02h d0 = lock status d1 = lock-down status read configuration register partition base address + 05h configuration register data extended configuration register partition base address + 06h extended configuration register data otp lock register 0 partition base address + 80h lock register 0 data otp block 0 C factory segment partition base address + 81h to 84h factory-programmed data otp block 1 C user-programmable segment partition base address + 85h to 88h user data otp lock register 1 partition base address + 89h lock register 1 data otp blocks 2C17 partition base address + 8ah to 109h user data read cfi issuing the read cfi command places the addressed partition in read cfi mode. sub- sequent reads from that partition output cfi information. the addressed partition remains in read cfi mode until a different read command is issued, or a program or erase operation is performed, or a block lock setup command is issued, which changes the read mode to read status register mode. the read cfi command functions independently of the voltage level on v pp . issuing the read cfi command to a partition that is actively programming or erasing changes that partitions read mode to read cfi mode. subsequent reads from that parti- tion will return invalid data until the program or erase operation has completed. read status register issuing the read status register command places the addressed partition in read status register mode; other partitions are not affected. subsequent reads from that par- tition output status register information. note: chip enable or output enable must be toggled to update the status register data. the addressed partition remains in read status register mode until a different read mode command is issued to that partition. performing a program, erase, or block lock operation also changes the partitions read mode to read status register mode. the read status register command functions independently of the voltage level on v pp . status register contents are valid only when sr[7]=1. 128mb, 256mb, 512mb, 1gb strataflash memory read operations pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 31 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. wait operation wait indicates the validity of output data during synchronous read operations. it is asserted when output data is invalid and de-asserted when output data is valid. wait changes state only on valid clock edges. upon power-up or exit from reset, wait de- faults to low true (rcr[10] = 0). wait is de-asserted during asynchronous reads. during write operations, wait is high-z on non-mux devices, and deasserted on ad-mux devices. table 18: wait behavior summary C non-mux device operation ce# oe# we# wait standby (device not selected) high x x high-z output disable low high high high-z synchronous read low low high active wait asserted = invalid data wait de-asserted = valid data asynchronous read low low high de-asserted write low high low high-z note: 1. this table does not apply to aadm devices. see aadm mode for wait behavior in aadm mode. table 19: wait behavior summary C ad mux device operation ce# oe# we# wait standby (device not selected) high x x high-z output disable low high high de-asserted synchronous read low low high active wait asserted = invalid data wait de-asserted = valid data asynchronous read low low high de-asserted write low high low de-asserted note: 1. this table does not apply to aadm devices. see aadm mode for wait behavior in aadm mode. 128mb, 256mb, 512mb, 1gb strataflash memory read operations pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 32 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. programming modes each programming region in a block can be configured for either control mode or ob- ject mode. the programming mode is automatically set based on the data pattern when a region is first programmed. selecting either control mode or object mode is done according to the specific needs of the system. in control mode, code or data is frequently changed (such as the flash file system or header information). in object mode, large code or data (such as objects or payloads) is infrequently changed. by implementing the appropriate programming mode, software can efficiently organize how information is stored in the memory array. control mode programming regions and object mode programming regions can be in- termingled within the same erase block. however, the programming mode of any region within a block can be changed only after erasing the entire block. control mode control mode programming is invoked when only the a-half (a3 = 0) of the program- ming region is programmed to 0s. the b-half (a3 = 1) remains erased. control mode al- lows up to 512 bytes of data to be programmed in the region. the information can be programmed in bits, bytes, or words. control mode supports the following programming methods: ? single-word programming (0041h) ? buffered programming (00e9h/00d0h) ? buffered enhanced factory programming (0080h/00d0h) when buffered programming is used in control mode, all addresses must be in the a- half of the buffer (a3 = 0). during buffer fill, the b-half (a3 = 1) addresses do not need to be filled with 0xffff. control mode programming is useful for storing dynamic information, such as flash file system headers, file info, and so on. typically, control mode programming does not re- quire the entire 512 bytes of data to be programmed at once. it may also contain data that is changed after initial programming using a technique known as bit twiddling. header information can be augmented later with additional new information within a control-mode-programmed region. this allows implementation of legacy file systems, as well as transaction-based power-loss recovery. in a control mode region, program operations can be performed multiple times. however, care must be taken to avoid programming any zeros in the b-half (a3 = 1) of the region. violation of this usage will cause sr[4] and sr[9] to be set, and the pro- gram operation will be aborted. 128mb, 256mb, 512mb, 1gb strataflash memory programming modes pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 33 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 10: configurable programming regions: control mode and object mode main array 256 programming regions of 1kb in each 256kb block 256kb 256kb 256kb . . 256kb 256kb . . . . . . . . . . . . . . . . . 256kb 256kb 256kb . . 256kb block programming region in object mode. programming region in control mode 512 bytes a half (control mode) 1kb address bit a3 = 1: allows up to 512 bytes of data to be programmed to the a half by bit, byte, or word. 512 bytes b half (erased) address bit a3 = 0: allows up to 1kb of data to be programmed. programming region in object mode programming region in object mode 1kb 1kb . . . object mode object mode programming is invoked when one or more bits are programmed to zero in the b-half of the programming region (a3 = 1). object mode allows up to 1kb to be stored in a programming region. multiple regions are used to store more than 1kb of information. if the object is less than 1kb, the un- used content will remain as 0xffff (erased). object mode supports the following programming methods: ? buffered programming (00e9h/00d0h) ? buffered enhanced factory programming (0080h/00d0h) single-word programming (0041h) is not supported in object mode. to perform multi- ple program operations within a programming region, control mode must be used. 128mb, 256mb, 512mb, 1gb strataflash memory programming modes pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 34 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. (object mode is useful for storing static information, such as objects or payloads, that rarely change.) once the programming region is configured in object mode, it cannot be augmented or overwritten without first erasing the entire block containing the region. subsequent program operations to a programming region configured in object mode will cause sr[4] and sr[8] to be set and the program operation to be aborted. issuing the 41h command to the b-half of an erased region will set error bits sr[8] and sr[9], and the program operation will not proceed. 128mb, 256mb, 512mb, 1gb strataflash memory programming modes pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 35 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 11: configurable programming regions: control mode and object mode segments 256kb block f f f f f f f f sequence table entry header f f f f f f f f header header object object object object object object object object object object 32 bytes 1kb program up to 1kb of data . . programming region in object mode 512 bytes b half (erased) 512 bytes a half (control mode) 1kb 16 bytes 16 bytes segments 31 30 ... 3 2 1 0 . . program up to 512 bytes of data programming region in control mode header header file information header header directory information sequence table entry f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f . . . segments 31 30 ... 3 2 1 0 128mb, 256mb, 512mb, 1gb strataflash memory programming modes pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 36 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. table 20: programming region next state command issued current state of programming region erased control mode object mode 0041h to b-half (a3 = 1) program fail; illegal com- mand sr[4,8,9] = 1 program fail; illegal com- mand sr[4,8,9] = 1 program fail; illegal com- mand sr[4,8,9] = 1 0041h to a-half (a3 = 0) program successful sr[4,8,9] = 0 region configured to control mode program successful sr[4,8,9] = 0 program fail; rewrite to object mode region sr[4,8] = 1 sr[9] = 0 00e9h to b-half (a3 = 1) program successful sr[4,8,9] = 0 region configured to object mode program fail; object data to control mode region sr[4,9] = 1 sr[8] = 0 program fail; rewrite to object mode region sr[4,8] = 1 sr[9] = 0 00e9h to a-half (a3 = 0) program successful sr[4,8,9] = 0 region configured to control mode program successful sr[4,8,9] = 0 program fail; rewrite to object mode region sr[4,8] = 1 sr[9] = 0 128mb, 256mb, 512mb, 1gb strataflash memory programming modes pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 37 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. program operations programming the array changes 1s to 0s. to change 0s to 1s, an erase operation must be performed. only one program operation can occur at a time. programming is per- mitted during erase suspend. information is programmed into the array by issuing the appropriate command. all program operations require the addressed block to be unlocked and a valid v pp voltage applied throughout the program operation. otherwise, the program opera- tion will abort, setting the appropriate status register error bit(s). if the device is deselected during a program or erase operation, the device continues to consume active power until the program or erase operation has completed. table 21: program command bus cycles command setup write cycle address bus setup write cycle data bus confirm write cycle address bus confirm write cycle data bus single-word program device address 0041h device address array data buffered program device address 00e9h device address 00d0h buffered enhanced factory program device address 0080h device address 00d0h single-word programming single-word programming is performed by issuing the single-word program com- mand. this is followed by writing the desired data at the desired address. the read mode of the addressed partition is automatically changed to read status register mode, which remains in effect until another read mode command is issued. issuing the read status register command to another partition switches that par- titions read mode to read status register mode, thereby allowing programming progress to be monitored from that partitions address. single-word programming is supported in control mode only. the array address speci- fied must be in the a-half of the programming region. during programming, the status register indicates a busy status (sr[7] = 0). upon com- pletion, the status register indicates a ready status (sr[7] = 1). the status register should be checked for any errors, then cleared. the only valid commands during programming are read array, read id, read cfi, and program suspend. after programming completes, any valid command can be issued. issuing the read array, read id, or read cfi command to a partition that is actively programming causes subsequent reads from that partition to output invalid data. valid data is output only after the program operation is complete. standby power levels are not realized until the program operation has completed. as- serting rst# immediately aborts the program operation, and array contents at the addressed location are indeterminate. the addressed block should be erased and the data reprogrammed. 128mb, 256mb, 512mb, 1gb strataflash memory program operations pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 38 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. buffered programming buffered programming programs multiple words simultaneously into the memory ar- ray. data is first written to a programming buffer and then programmed into the array in buffer-sized increments, significantly reducing the effective word programming time. optimal performance and power consumption is realized only by aligning the starting address to buffer-sized boundaries within the array. crossing a buffer-sized boundary can cause the buffered programming time to double. the buffered program operation consists of the following fixed, predefined se- quence of bus write cycles: 1) issue the setup command; 2) issue a word count; 3) fill the buffer with user data; and 4) issue the confirm command. once the setup command has been issued to an address, subsequent bus write cycles must use ad- dresses within the same block throughout the operation; otherwise, the operation will abort. bus read cycles are allowed at any time and at any address. note: v pp must be at v ppl or v pph throughout the buffered program operation. upon programming completion, the status register indicates ready (sr7 = 1), and any valid command may be issued. a full status register check should be performed to check for any programming errors. if any error bits are set, the status register should be cleared using the clear status register command. a subsequent buffered program operation can be initiated by issuing another set- up command and repeating the buffered programming sequence. any errors in the sta- tus register caused by a previous operation should first be cleared to prevent masking of errors that may occur during a subsequent buffered program operation. valid commands issued to the busy partition during array programming are read ar- ray, read id, read cfi, read status, and program suspend. issuing the read array, read id, or read cfi command to a partition that is actively programming causes subsequent reads from that partition to output invalid data. valid data is output only after the program operation has completed. buffered enhanced factory programming buffered enhanced factory programming (befp) improves programming performance through the use of the write buffer, elevated programming voltage (v pph ), and en- hanced programming algorithm. user data is written into the write buffer, and then the buffer contents are automatically written into the array in buffer-sized increments. internal verification during programming (inherent to mlc technology) and status reg- ister error checking are used to determine proper completion of the program opera- tion. this eliminates delays incurred when switching between single-word pro- gram and verify operations. befp consists of the following three distinct phases: 1. setup phase: v pph and block lock checks 2. program/verify phase: buffered programming and verification 3. exit phase: block error check befp is supported in both control mode and object mode. the programming mode se- lection for the entire array block is driven by the specific type of information, such as header or object data. header/object data is aligned on a 1kb programming region boundary in the main array block. 128mb, 256mb, 512mb, 1gb strataflash memory program operations pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 39 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. table 22: befp requirements and considerations befp requirements temperature (t case ) must be 25 c, 5 c voltage on vcc must be within the allowable operating range voltage on vpp must be within the allowable operating range block being programmed must be erased and unlocked befp considerations block cycling below 100 erase cycles reading from another partition during efp (rww) is not allowed befp programs within one block at a time befp cannot be suspended befp setup phase issuing the befp setup and confirm command sequence starts the befp algorithm. the read mode of the addressed partition is automatically changed to read status regis- ter mode. the address used when issuing the setup and confirm commands must be buffer- size aligned within the block being programmed; buffer contents cannot cross block boundaries. note: the read status register command must not be issued; it will be interpreted as data to be written to the write buffer. a setup delay ( t befp/setup) occurs while the internal algorithm checks v pp and block lock status. if errors are detected, the appropriate status register error bits are set and the operation aborts. the status register should be polled for successful befp setup, indicated by sr[7:0] = 0 (device busy, buffer ready for data). befp program/verify phase data is first written into the write buffer, then programmed into the array. during the buffer fill sequence, the address used must be buffer-size aligned. use of any other ad- dress will cause the operation to abort with a program fail error, and any data previously loaded in the buffer will not be programmed into the array. the buffer fill data is stored in sequential buffer locations starting at address 00h. a word count equal to the maximum buffer size is used; therefore, the buffer must be completely filled. if the amount of data is less than the maximum buffer size, the re- maining buffer locations must be padded with ffffh to completely fill the buffer. array programming starts as soon as the write buffer is full. data words from the write buffer are programmed into sequential array locations. sr0 = 1 indicates the write buf- fer is not available while the befp algorithm programs the array. the status register should be polled for sr0 = 0 (buffer ready for data) to determine when the array programming has completed and the write buffer is again available for loading. the internal address is automatically incremented to enable subsequent array programming to continue from where the previous buffer-fill/array program sequence ended within the block. this cycle can be repeated to program the entire block. befp exit phase to exit the program/verify phase, write ffffh to an address outside of the block. 128mb, 256mb, 512mb, 1gb strataflash memory program operations pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 40 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. the status register should be polled for sr7 = 1 (device ready), indicating the befp algo- rithm has finished running and the device has returned to normal operation. a full status register error check should be performed to ensure the block was program- med successfully. 128mb, 256mb, 512mb, 1gb strataflash memory program operations pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 41 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. erase operations block erase erasing a block changes 0s to 1s. to change 1s to 0s, a program operation must be performed. erasing is performed on a block basis; an entire block is erased each time an erase command sequence is issued. once a block is fully erased, all addressable loca- tions within that block read as logical 1s (ffffh). only one block erase operation can occur at a time. a block erase operation is not permitted during program suspend. all block erase operations require the ad- dressed block to be unlocked, and v pp must be at v ppl or v pph throughout the block erase operation. otherwise, the operation aborts, setting the appropriate status regis- ter error bit(s). to perform a block erase operation, issue the block erase setup command at the desired block address. the read mode of the addressed partition automatically changes to read status register mode and remains in effect until another read mode command is issued. the erase confirm command latches the address of the block to be erased. the ad- dressed block is preconditioned (programmed to all 0s), erased, and then verified. issuing the read status register command to another partition switches that par- titions read mode to the read status register, thereby allowing block erase progress to be monitored from that partitions address. sr0 indicates whether the addressed partition or the other partition is erasing. during a block erase operation, the status register indicates a busy status (sr[7] = 0). issuing the read array command to a partition that is actively erasing a main block causes subsequent reads from that partition to output invalid data. valid array data is output only after the block erase operation has finished. upon completion, the status register indicates a ready status (sr[7] = 1). the status reg- ister should be checked for any errors, and then cleared. if the device is deselected during an erase operation, the device continues to consume active power until the erase operation is completed. asserting rst# immediately aborts the block erase operation, and array contents at the addressed location are indeterminate. the addressed block should be erased again. the only valid commands during a block erase operation are read array, read id, read cfi, and erase suspend. after the block erase operation has completed, any valid command can be issued. table 23: erase command bus cycle command setup write cycle address bus setup write cycle data bus confirm write cycle address bus confirm write cycle data bus block erase device address 0020h block address 00d0h 128mb, 256mb, 512mb, 1gb strataflash memory erase operations pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 42 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. suspend and resume operations program and erase operations of the main array can be suspended to perform other device operations, and then subsequently resumed. otp area programming operations cannot be suspended. during erase suspend or program suspend, the addressed block must remain unlocked, v pp must be at v ppl or v pph , and wp# must remain unchanged. otherwise, the erase or program operation will abort, setting the appropriate status register error bit(s). suspend operation to suspend an ongoing erase or program operation, issue the suspend command to any device address. issuing the suspend command does not change the read mode. upon issuing a suspend command, the ongoing erase or program operation sus- pends after a delay of t susp. the operation is suspended only when sr[7:6] = 1 (erase suspend) or sr[7:2] = 1 (program suspend). while suspended, reading from a block that was being erased or programmed is not al- lowed. also, programming within an erase suspended block is not allowed, and if at- tempted, will result in a programming error (sr[4] = 1). erasing under program suspend is not allowed. however, array programming under erase suspend is allowed, and can also be suspended. this results in a simultaneous erase suspend and program suspend condition, indicated by sr[7:6,2] = 1. additional valid commands while suspended are read array, read status register, read id, read cfi, clear status regis- ter, and resume. no other commands are allowed. during suspend, ce# may be de-asserted, placing the device in standby and reducing active current to standby levels. v pp must remain at v ppl or v pph , and wp# must remain unchanged. asserting rst# aborts any suspended block erase and program operations; array contents at the addressed locations will be indeterminate. during suspend, ce# may be de-asserted. the device is placed in standby, reducing ac- tive current. v pp must remain at v ppl or v pph , and wp# must remain unchanged. asserting rst# aborts suspended block erase and program operations; array con- tents at the addressed locations are indeterminate. table 24: valid commands during suspend device command program suspend erase suspend read array allowed allowed read status register allowed allowed clear status register allowed allowed read device information allowed allowed cfi query allowed allowed word program not allowed allowed buffered program not allowed not allowed buffered enhanced factory program not allowed not allowed block erase not allowed not allowed 128mb, 256mb, 512mb, 1gb strataflash memory suspend and resume operations pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 43 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. table 24: valid commands during suspend (continued) device command program suspend erase suspend program/erase suspend not allowed not allowed program/erase resume allowed allowed resume operation to resume a suspended erase or program operation, issue the resume command to any device address. the erase or program operation continues where it left off, and the respective status register suspend bit is cleared. issuing the resume command does not change the read mode. when the resume command is issued during a simultaneous erase suspend or pro- gram suspend condition, the program operation is resumed first. upon completion of the program operation, the status register should be checked for any errors, and cleared if needed. the resume command must be issued again to complete the erase operation. upon completion of the erase operation, the status register should be checked for any errors, and cleared if needed. table 25: suspend and resume command bus cycles command setup write cycle address bus setup write cycle data bus confirm write cycle address bus confirm write cycle data bus suspend device address 00b0h C C resume device address 00d0h C C 128mb, 256mb, 512mb, 1gb strataflash memory suspend and resume operations pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 44 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. blank check operation blank check verifies whether a main-array block is completely erased. a blank check operation is performed one block at a time, and cannot be used during program sus- pend or erase suspend. to use blank check, first issue the blank check setup command followed by the confirm command. the read mode of the addressed partition is automatically changed to read status register mode, which remains in effect until another read mode is issued. during a blank check operation, the status register indicates a busy status (sr[7] = 0). upon completion, the status register indicates a ready status (sr[7] = 1). issuing the read status register command to another partition switches that partitions read mode to read status register mode, thereby allowing the blank check operation to be monitored from that partitions address. the status register should be checked for any errors, and then cleared. if theblank check operation fails (the block is not completely erased), then the status register will indicate a blank check error (sr[7:5] = 1). the only valid command during a blank check operation is read status. blank check cannot be suspended. after the blank check operation has completed, any valid command can be issued. table 26: blank check command bus cycles command setup write cycle address bus setup write cycle data bus confirm write cycle address bus confirm write cycle data bus blank check block address 00bch block address 00d0h 128mb, 256mb, 512mb, 1gb strataflash memory blank check operation pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 45 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. block lock two methods of block lock control are available: software and hardware. software con- trol uses the block lock and block unlock commands. hardware control uses the block lock-down command along with asserting wp#. upon power-up or exit from reset, all main array blocks are locked, but not locked down. locked blocks cannot be erased or programmed. block lock and unlock operations are independent of the voltage level on v pp . to lock, unlock, or lock-down a block, first issue the setup command to any address within the desired block. the read mode of the addressed partition is automatically changed to read status register mode. next, issue the desired confirm command to the blocks address. note that the confirm command determines the operation per- formed. the status register should be checked for any errors, and then cleared. the lock status of a block can be determined by issuing the read id command, and then reading from the blocks base address + 02h. see the table below table for the lock- bit settings. blocks cannot be locked or unlocked while being actively programmed or erased. blocks can be locked or unlocked during erase suspend, but not during program sus- pend. if a block erase operation is suspended, and then the block is locked or locked down, the lock status of the block will be changed immediately. when resumed, the erase operation will still complete. block lock-down protection is dependent on wp#. a locked-down block can only be un- locked by issuing the block unlock command with wp# de-asserted. to return an unlocked block to the locked-down state, a block lock-down command must be is- sued prior to asserting wp#. when wp# = v il , blocks locked down are locked, and cannot be unlocked using the block unlock command. when wp# = v ih , block lock-down protection is disabled; locked-down blocks can be individually unlocked using the block unlock command. subsequently, when wp# = v il , previously locked-down blocks are once again locked and locked-down, including locked-down blocks that may have been unlocked while wp# was de-asserted. issuing the block lock-down command to an unlocked block does not lock the block. however, asserting wp# after issuing the block lock-down command locks (and locks down) the block. lock-down for all blocks is only cleared upon power-up or exit from reset. table 27: block lock command bus cycles command setup write cycle address bus setup write cycle data bus confirm write cycle address bus confirm write cycle data bus block lock block address 0060h block address 0001h block un- lock block address 0060h block address 00d0h 128mb, 256mb, 512mb, 1gb strataflash memory block lock pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 46 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. table 27: block lock command bus cycles (continued) command setup write cycle address bus setup write cycle data bus confirm write cycle address bus confirm write cycle data bus block lock- down block address 0060h block address 002fh table 28: block lock configuration block lock configu- ration block base address bit block is unlocked block base address = 0x02 dq0 = 0b0 block is locked block base address = 0x02 dq0 = 0b1 block is not locked down block base address = 0x02 dq1 = 0b0 block is locked down block base address = 0x02 dq1 = 0b1 figure 12: block lock operations locked [x, 0, 1] unlocked [x, 0, 0] locked down [0, 1, 1] software locked [1, 1, 1] hardware locked [0, 1, 1] unlocked [1, 1, 0] power-up or exit from reset software control (lock, unlock, lock-down command) hardware control (wp#) notes: 1. the [n,n,n] denotes logical state of wp#, dq1,and dq0, respectively; x = "dont care." 2. the [0,1,1] states should be tracked by system software to differentiate between the hardware-locked state and the lock-down state. 128mb, 256mb, 512mb, 1gb strataflash memory block lock pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 47 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. one-time programmable operations the device contains sixteen 128-bit one-time programmable (otp) blocks, two 64-bit otp blocks, and two 16-bit otp lock registers. otp lock register 0 is used for locking otp blocks 0 and 1 (two 64-bit blocks), and otp lock register 1 is used for locking otp blocks 2 through 17 (sixteen 128-bit blocks). each block contains otp bits that are factory set to 1 and can only be programmed from 1 to 0; otp block bits cannot be erased from 0 back to 1. this feature makes the otp blocks particularly useful for implementing system-level security schemes, permanent- ly storing data, or storing fixed system parameters. otp block 0 is pre-programmed with a unique 64-bit value and locked at the factory. otp block 1 contains all 1s and is user-programmable. otp blocks 1 through 16 contain all 1s and are user-programmable. each otp block can be accessed multiple times to program individual bits, as long as the block remains unlocked. when a lock register bit is programmed, the associated otp block can only be readit can no longer be programmed. otp lock register bits lock out subsequent programming of the corresponding otp block. each otp block can be locked by programming its corresponding lock bit to 0. as long as an otp block remains unlocked (that is, its lock bit = 1), any of its remaining 1 bits can be programmed to 0. note: once an otp block is locked, it cannot be unlocked. attempts to program a locked otp block will fail with error bits set. additionally, because the lock register bits themselves are otp, when programmed, lock register bits cannot be erased. therefore, when an otp block is locked, it cannot be unlocked. table 29: program otp area command bus cycles command setup write cycle address bus setup write cycle data bus confirm write cycle address bus confirm write cycle data bus program otp area device address 00c0h otp register address register data 128mb, 256mb, 512mb, 1gb strataflash memory one-time programmable operations pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 48 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 13: otp area map 0 x 8 9 otp lo c k r eg i s t e r 1 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 0 x 10 2 0 x 10 9 0 x 8 a 0 x 9 1 1 28- b i t otp 1 7 ( u s e r - p r og r am m ab l e ) 1 28- b i t otp block 2 ( u s e r - p r og r am m ab l e ) 0 x 8 8 0 x 8 5 64- b i t otp block 1 ( u s e r - p r og r am m ab l e ) 0 x 8 4 0 x 8 1 0 x 8 0 otp l o ck r eg i st e r 0 64- b i t otp block 0 ( f a c to r y - p rog r am m ed ) 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 128mb, 256mb, 512mb, 1gb strataflash memory one-time programmable operations pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 49 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. programming otp area otp area programming is performed 16 bits at a time; only zeros within the data word affect any change to the otp bits. to program any otp blocks or lock registers, first issue the program otp area set- up command at any device address. the read state of that partition changes to read sta- tus. next, write the desired otp data at the desired otp address. attempting to program outside of the otp area causes a program error (sr[4] = 1). attempting to program a locked otp block causes a program error and a lock error (sr[4] = 1, sr[1] = 1). otp area programming cannot be suspended. dual operations between the parameter partition and the otp area are not allowed. reading otp area the otp area is read from within the address space of any partition. to read from the otp area. the following must be done: 1. issue the read id command at the address of any partition to place that partition in the read id state. 2. perform a read operation at the base address of that partition, plus the address offset corresponding to the otp word to be read. data is read 16 bits at a time. if a program or erase operation occurs within the device while it is reading from the otp area, certain restrictions may apply. 128mb, 256mb, 512mb, 1gb strataflash memory one-time programmable operations pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 50 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. global main-array protection global main-array protection can be implemented by controlling v pp . when program- ming or erasing main-array blocks, v pp must be equal to or greater than v ppl, min . when v pp is below v pplk , program or erase operations are inhibited, thus providing abso- lute protection of the main array. various methods exist for controlling v pp , ranging from simple logic control to off-board voltage control. the following figure shows example v pp supply connections that can be used to support program or erase operations and main-array protection. figure 14: v pp supply connection example v cc v cc v pph v ppl v pp ? factory programming: v pp = v pph ? program/erase protection: v pp v pplk v cc v cc prot# v pp ? program/erase enable: prot# = v ih ? program/erase protection: prot# = v il v cc v cc v pp ? low-voltage programming or ? factory programming v cc v cc v pp ? low-voltage programming: v pp = v cc ? program/erase protection: none 10k v ppl v ppl v pph 128mb, 256mb, 512mb, 1gb strataflash memory global main-array protection pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 51 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. dual operation multipartition architecture of the device enables reading from one partition while a program or erase operation is occurring in another partition. this is called read- while-program and read-while-erase, respectively. only status reads are allowed from a partition that is busy programming or erasing. if non-status reads are required from a partition that is busy programming or erasing, the program or erase operation must be suspended first. table 30: dual operation restrictions the following table shows the allowed dual operations between array operations and non-array operations read program or erase main partition program otp area main partition yes (except busy partition) yes (except busy partition) status yes yes id, otp, or cfi yes (except busy partition) no 128mb, 256mb, 512mb, 1gb strataflash memory dual operation pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 52 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. power and reset specifications initialization proper device initialization and operation is dependent on the power-up/down se- quence, reset procedure, and adequate power-supply decoupling. power-up and down to avoid conditions that may result in spurious program or erase operations, the power sequences shown below are recommended. note that each power supply must be at its minimum voltage range before applying or removing the next supply voltage in the sequence. also, device inputs must not be driven until all supply voltages have at- tained their minimum range, and rst# should be low during all power transitions. when powering down the device, voltages should reach 0v before power is reapplied to ensure proper device initialization. otherwise, indeterminate operation could result. when v ccq goes below v lkoq , the device is reset. table 31: power sequencing power supply power-up sequence power-down sequence v cc,min first first first 1 first 1 third second second 1 second 1 v ccq,min second second 1 first 1 second second first 1 second 1 first v pp,min third second 1 second first 1 first first 1 first second 1 note: 1. connected/sequenced together. reset during power-up and power-down, rst# should be asserted to prevent spurious pro- gram or erase operations. while rst# is low, device operations are disabled, all in- puts such as address and control are ignored, and all outputs such as data and wait are placed in high-z. invalid bus conditions are effectively masked out. upon power-up, rst# can be de-asserted after t vccph, allowing the device to exit from reset. upon exiting from reset, the device defaults to asynchronous read array mode, and the status register defaults to 0080h. array data is available after t phqv, or a bus write cycle can begin after t phwl. if rst# is asserted during a program or erase operation, the operation will abort and array contents at that location will be invalid. for proper system initialization, connect rst# to the low true reset signal that asserts whenever the processor is reset. this will ensure the device is in the expected read mode (read array) upon startup. 128mb, 256mb, 512mb, 1gb strataflash memory power and reset specifications pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 53 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 15: reset operation waveforms (a) reset during read mode v ih v il rst# (d) v cc power-up to rst# high t plph t phqv t phqv t phqv v cc 0v v cc t vccph (b) reset during program or block erase p1 p2 v ih v il rst# abort complete abort complete t plrh (c) reset during program or block erase p1 3 p2 v ih v il rst# t plrh table 32: reset specifications note 1 applies to all parameter symbol min max unit notes rst# pulse width low t plph 100 C ns 2, 3, 6 rst# low to device reset during erase t plrh C 25 s 3, 6 rst# low to device reset during program C 25 3, 6 v cc power valid to rst# de-asser- tion (high) t vccph 300 C 4, 5 notes: 1. these specifications are valid for all packages and speeds, and are sampled, not 100% tested. 2. the device might reset if t plph is < t plph min, but this is not guaranteed. 3. not applicable if rst# is tied to v ccq . 4. if rst# is tied to the v cc supply, the device is not ready until t vccph after v cc v cc,min . 5. if rst# is tied to any supply/signal with v ccq voltage levels, the rst# input voltage must not exceed v cc until v cc v cc,min . 6. reset completes within t plph if rst# is asserted while no erase or program operation is executing. 128mb, 256mb, 512mb, 1gb strataflash memory power and reset specifications pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 54 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. automatic power saving automatic power saving provides low-power operation following reads during active mode. after data is read from the memory array and the address lines are quiescent, au- tomatic power savings automatically places the device into standby. in automatic power savings, device current is reduced to i ccaps . power supply decoupling flash memory devices require careful power supply decoupling to prevent external transient noise from affecting device operations, and to prevent internallygenerated transient noise from affecting other devices in the system. ceramic chip capacitors of 0.01f to 0.1f should be used between all v cc , v ccq , and v pp supply connections and system ground. these high-frequency, inherently low-in- ductance capacitors should be placed as close as possible to the device package, or on the opposite side of the printed circuit board close to the center of the device package footprint. larger (4.7f to 33.0f) electrolytic or tantulum bulk capacitors should also be distrib- uted as needed throughout the system to compensate for voltage sags and surges caused by circuit trace inductance. transient current magnitudes depend on the capacitive and inductive loading on the devices outputs. for best signal integrity and device performance, high-speed design rules should be used when designing the printed-circuit board. circuit-trace impedan- ces should match output-driver impedance with adequate ground-return paths. this will help minimize signal reflections (overshoot/undershoot) and noise caused by high- speed signal edge rates. 128mb, 256mb, 512mb, 1gb strataflash memory power and reset specifications pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 55 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. electrical specifications stresses greater than those listed may cause permanent damage to the device. this is a stress rating only. exposure to absolute maximum rating and operating conditions for extended periods may adversely affect reliability. stressing the device beyond the abso- lute maximum ratings may cause permanent damage. these are stress ratings only. table 33: absolute maximum ratings parameter min max units notes temperature under bias (t a ) C30 85 c 5 storage temperature (t a ) C65 125 c 5 v pp voltage C2.0 11.5 v 1, 2, 3 v cc voltage C2.0 v ccq + 2.0 v 1 voltage on any input/output signal (except v cc , v ccq , and v pp ) C2.0 v ccq + 2.0 v 2 v ccq voltage C0.2 v ccq + 2.0 v 1 v pph time C 80 hours 3 output short circuit current C 100 ma 4 block program/erase cycles: main blocks 100,000 C cycles 3 notes: 1. voltages shown are specified with respect to v ss . during transitions, the voltage poten- tial between v ss and input/output and supply pins may undershoot to C1.0v for periods less than 20ns and may overshoot to v cc q (max) + 1.0v for periods less than 20ns. 2. voltages shown are specified with respect to v ss . during transitions, the voltage poten- tial between v ss and supply pins may undershoot to C2.0v for periods less than 20ns and may overshoot to v cc (max) + 2.0v for periods less than 20ns. 3. operation beyond this limit may degrade performance. 4. output shorted for no more than one second; no more than one output shorted at a time. 5. temperature specified is ambient (t a ), not case (t c ). table 34: operating conditions symbol parameter min max units notes t c operating temperature C30 85 c 1 v cc v cc supply voltage 1.7 2.0 v v ccq i/o supply voltage 1.7 2.0 v v ppl v pp voltage supply (logic level) 0.9 2.0 v v pph factory programming v pp 8.5 9.5 v note: 1. t c = case temperature, not ambient. 128mb, 256mb, 512mb, 1gb strataflash memory electrical specifications pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 56 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. electrical specifications C dc current and voltage characteristics and operating conditions table 35: dc current characteristics and operating conditions parameter symbol conditions litho (nm) density (mbit) 1.7 v - 2.0 v unit notes typ max input load, output leakage, standby input load current i li v cc = v cc,max ; v ccq = v ccq,max ; v in = v ccq or v ss C C C 1 a 1 output leakage current i lo v cc = v cc,max ; v ccq = v ccq,max ; v in = v ccq or v ss C C C 1 a 1 v cc standby i ccs , i ccd v cc = v cc,max ; v ccq = v ccq,max ; ce# = v ccq ; rst# = v ccq or gnd (for i ccs ); wp# = v ih 90 256 512 35 50 95 120 a 1, 2 65 128 256 512 1024 45 50 60 70 115 130 160 185 45 128 256 512 1024 18 18 18 20 100 100 100 140 average vcc read average v cc read current; asychronous sin- gle-word read; f = 5 mhz; 1 clk i ccr v cc = v cc,max ; ce# = v il ; oe# = v ih ; inputs: v il or v ih C C 25 30 ma 1, 3, 4 average v cc read current; page mode read; f = 13 mhz; 17 clk; burst = 16- word i ccr v cc = v cc,max ; ce# = v il ; oe# = v ih ; inputs: v il or v ih C C 11 15 ma 1, 3, 4 average v cc read current; sychronous burst read; f = 66 mhz; lc = 7; burst = 8-word burst = 16-word; burst = continu- ous i ccr v cc = v cc,max ; ce# = v il ; oe# = v ih ; inputs: v il or v ih C C 22 19 25 32 26 34 ma 1, 3, 4 128mb, 256mb, 512mb, 1gb strataflash memory electrical specifications C dc current and voltage characteris- tics and operating conditions pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 57 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. table 35: dc current characteristics and operating conditions (continued) parameter symbol conditions litho (nm) density (mbit) 1.7 v - 2.0 v unit notes typ max average v cc read current; sychronous burst read; f = 108 mhz; lc = 10; burst = 8-word burst = 16-word; burst = continu- ous i ccr v cc = v cc,max ; ce# = v il ; oe# = v ih ; inputs: v il or v ih C C 26 23 30 36 30 42 ma 1, 3, 4 average v cc read current; sychronous burst read; f = 133 mhz; lc = 13; burst = 8-word burst = 16-word; burst = continu- ous i ccr v cc = v cc,max ; ce# = v il ; oe# = v ih ; inputs: v il or v ih C C 26 24 33 35 33 46 ma 1, 3, 4 vcc program, erase, blank check v cc program v cc erase v cc blank check i ccw , i cce , i ccbc v pp = v ppl or v pp = v pph ; program/erase in progress C C 35 50 ma 1, 3, 4, 5 v cc program sus- pend v cc erase sus- pend i ccws , i cces ce# = v ccq ; suspend in progress 90 256 512 35 50 95 120 a 1, 3, 6 65 128 256 512 1024 45 50 60 70 115 130 160 185 45 128 256 512 1024 18 18 18 20 100 100 100 140 vpp program, read, erase, blank check, standby v pp standby cur- rent; v pp pro- gram suspend current; v pp erase suspend current i pps , i ppws , i ppes v pp = v ppl ; suspend in progress C C 0.2 5 a 3 v pp read i ppr v pp v cc C C 2 15 a 3 v pp program cur- rent i ppw v pp = v ppl = v pph ; pro- gram in progress C C 0.05 0.10 ma 3 v pp erase current i ppe v pp = v ppl = v pph ; erase in progress C C 0.05 0.10 ma 3 128mb, 256mb, 512mb, 1gb strataflash memory electrical specifications C dc current and voltage characteris- tics and operating conditions pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 58 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. table 35: dc current characteristics and operating conditions (continued) parameter symbol conditions litho (nm) density (mbit) 1.7 v - 2.0 v unit notes typ max v pp blank check current i ppbc v pp = v ppl = v pph ; blank check in progress C C 0.05 0.10 ma 3 automatic power savings automatic pow- er savings i ccaps v cc = v cc,max ; v ccq = v ccq,max ; ce# = v ssq ; rst# = v ccq ; all inputs are at rail-to-rail (v ccq or v ssq ) 90 256 512 35 50 95 120 a C 65 128 256 512 1024 45 50 60 70 115 130 160 185 45 128 256 512 1024 18 18 18 20 100 100 100 140 notes: 1. all currents are rms unless noted. typical values at typical v ccq , t c = +25c. 2. i ccs is the average current measured over any 5ms time interval 5s after ce# is de-asser- ted. 3. sampled, not 100% tested. 4. v cc read + program current is the sum of v cc read and v cc program currents. v cc read + erase current is the sum of v cc read and v cc erase currents. 5. i ccw , i cce is measured over typical or max times specified in program and erase charac- teristics. 6. i cces is specified with the device deselected. if the device is read while in erase suspend, current is i cces + i ccr . 128mb, 256mb, 512mb, 1gb strataflash memory electrical specifications C dc current and voltage characteris- tics and operating conditions pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 59 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. table 36: dc voltage characteristics and operating conditions parameter symbol conditions v ccq = 1.7v - 2.0v unit notes min max input low voltage v il C 0 0.45 v 1 input high voltage v ih C v ccq - 0.45 v ccq v 1 output low voltage v ol v cc = v cc,min ; v ccq = v ccq,min ; i ol = 100a C 0.1 v output high voltage v oh v cc = v cc,min ; v ccq = v ccq,min ; i ol = 100a v ccq - 0.1 C v v pp lockout voltage v pplk C C 0.4 v 2 v cc lock voltage v lko C 1.0 C v v ccq lock voltage v lkoq C 0.9 C v notes: 1. input voltages can undershoot to C1.0v and overshoot to v ccq + 1v for durations of 2ns or less. 2. v pp < v pplk inhibits erase and program operations. do not use v ppl and v pph outside of their valid ranges. 128mb, 256mb, 512mb, 1gb strataflash memory electrical specifications C dc current and voltage characteris- tics and operating conditions pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 60 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. electrical specifications C ac characteristics and operating conditions ac test conditions figure 16: ac input/output reference waveform t rise/fall v ccq /2 input v ccq /2 output v ccq 0v test points note: 1. ac test inputs are driven at v ccq for logic 1, and 0.0v for logic 0. input/output timing begins/ends at v ccq /2. input rise and fall times (10% to 90%) <5ns. worst-case speed oc- curs at v cc = v cc,min . table 37: ac input requirements parameter symbol frequency min max unit condition inputs rise/fall time (address, clk, ce#, oe#, adv#, we#, wp#) t rise/fall @133 mhz, 108 mhz 0.3 1.2 ns v il to v ih or v ih to v il @66 mhz 0 3 address-address skew 1 t askw 0 3 ns @v ccq /2 note: 1. for an address to be latched the skew is defined as the time when the first address bit is valid to the last address bit going valid. figure 17: transient equivalent testing load circuit device under test out c l notes: 1. see test configuration load capacitor values for worst case speed conditions table for component values for the test configurations. 2. c l includes jig capacitance. table 38: test configuration load capacitor values for worst case speed conditions test configuration c l (pf) 1.7v standard test 30 2.0v standard test 30 128mb, 256mb, 512mb, 1gb strataflash memory electrical specifications C ac characteristics and operating conditions pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 61 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 18: clock input ac waveform t fclk/rclk clk t ch/cl v ih v il t clk table 39: capacitance notes 1, 2, and 3 apply to all parameters parameter symbol signals min typ max unit test condition input capacitance c in address, clk, ce#, oe#, adv#, we#, wp#, dpd, and rst# 2 4 6 pf v in = 0C2.0v output capaci- tance c out data, wait 2 5 6 pf v out = 0C2.0v notes: 1. tc = +25c, f = 1 mhz. 2. sampled, not 100% tested. 3. silicon die capacitance only. for discrete packages, add 1pf. for stacked packages, total capacitance = 2pf + sum of silicon die capacitances. 128mb, 256mb, 512mb, 1gb strataflash memory electrical specifications C ac characteristics and operating conditions pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 62 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. ac read specifications ac read specifications (clk-latching, 133 mhz) table 40: ac read specifications (clk-latching, 133 mhz), v ccq = 1.7v to 2.0v note 1 applies to all parameters parameter symbol 96ns unit notes min max asynchronous specifications read cycle time t avav 96 C ns address to output valid t avqv C 96 ns ce# low to output valid t elqv C 96 ns oe# low to output valid t glqv C 7 ns 2 rst# high to output valid t phqv C 150 ns ce# low to output in low-z t elqx 0 C ns 3 oe# low to output in low-z t glqx 0 C ns 2, 3 ce# high to output in high-z t ehqz C 7 ns 3 oe# high to output in high-z t ghqz C 7 ns 3 output hold from first occurring address, ce#, or oe# change t oh 0 C ns 3 ce# pulse width high t ehel 7 C ns ce# low to wait valid t eltv C 8 ns ce# high to wait high-z t ehtz C 7 ns 3 oe# high to wait valid (a/d mux only) t ghtv C 5.5 ns oe# low to wait valid t gltv C 5.5 ns oe# low to wait in low-z t gltx 0 C ns 3 oe# high to wait in high-z (non-mux only) t ghtz 0 7 ns 3 latching specifications address setup to adv# high t avvh 5 C ns ce# low to adv# high t elvh 7 C ns adv# low to output valid t vlqv C 96 ns adv# pulse width low t vlvh 7 C ns adv# pulse width high t vhvl 7 C ns address hold from adv# high t vhax 5 C ns adv# high to oe# low (a/d mux only) t vhgl 2 C ns page address access (non-mux only) t apa C 15 ns rst# high to adv# high t phvh 30 C ns clock specifications clk frequency f clk C 133 mhz clk period t clk 7.5 C ns clk high/low time t ch/cl 0.45 0.55 clk period 128mb, 256mb, 512mb, 1gb strataflash memory ac read specifications pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 63 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. table 40: ac read specifications (clk-latching, 133 mhz), v ccq = 1.7v to 2.0v (continued) note 1 applies to all parameters parameter symbol 96ns unit notes min max clk fall/rise time t fclk/rclk 0.3 1.2 ns synchronous specifications address setup to clk high t avch 2 C ns adv# low setup to clk high t vlch 2 C ns ce# low setup to clk high t elch 2.5 C ns clk to output valid t chqv C 5.5 ns output hold from clk high t chqx 2 C ns address hold from clk high t chax 2 C ns clk high to wait valid t chtv C 5.5 ns adv# high hold from clk t chvl 2 C ns wait hold from clk t chtx 2 C ns adv# hold from clk high t chvh 2 C ns 4 clk to oe# low (a/d mux only) t chgl 2 C ns read access time from address latching clock t acc 96 C ns adv# pulse width low for sync reads t vlvh 1 2 clocks 4 adv# high to clk high t vhch 2 C ns 4 notes: 1. see electrical specifications C ac characteristics and operating conditions for timing measurements and max allowable input slew rate. 2. oe# can be delayed by up to t elqv - t glqv after the ce# falling edge without impact to t elqv. 3. sampled, not 100% tested. 4. for 45nm devices, these specifications are not required as a result of the enhanced clk- latching scheme. see the strataflash ? cellular memory 65nm to 45nm m family migra- tion guide and the strataflash ? cellular memory 65nm to 45nm m family latching scheme migration guide for more information. ac read timing the synchronous read timing waveforms apply to both 108 and 133 mhz devices. how- ever, devices that only support up to 108 mhz need not meet the following timing spec- ifications. ? t chvh ? t chgl ? t acc ? t vlvh ? t vhch note: the wait signal polarity in all the timing waveforms is low-true (rcr10 = 0). wait is shown as de-asserted with valid data (rcr8 = 0). wait is de-asserted during asynchronous reads. 128mb, 256mb, 512mb, 1gb strataflash memory ac read specifications pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 64 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 19: asynchronous page-mode read (non-mux) a[max:4] a[3:0] adv# t avav t avqv t vlqv t vhax t avvh t phvh t vlvh t vhvl ce# oe# wait dq[15:0] t phqv t ghqz t ehqz t oh t apa t glqx t elqx t elvh t eltv t gltv t gltx t apa t oh t oh t apa t oh rst# t elqv t ehel t ehtz t glqv t ghtz note: 1. wait shown active low (rcr[10] = 0). 128mb, 256mb, 512mb, 1gb strataflash memory ac read specifications pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 65 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 20: synchronous 8- or 16-word burst read (non-mux) a[max:0] clk adv# latency count ce# oe# wait dq[15:0] t chvh t vlch t avch t chax t chtv t chqv t elch t gltx t chqv t chtx t chqx t clk t ch t cl rst# t chqv t chqx t chtv t gltv t chvl notes: 1. 8-word and 16-word burst are always wrap-only. 2. wait shown as active low (rcr[10] = 0) and asserted with data (rcr[8] = 0). 3. adv# may be held low throughout the synchronous read operation. 4. t avqv, t elqv, and t vlqv apply to legacy-latching only. 5. t acc and t vlvh apply to clock-latching only. 128mb, 256mb, 512mb, 1gb strataflash memory ac read specifications pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 66 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 21: synchronous continuous misaligned burst read (non-mux) a[max:0] clk adv# latency count ce# oe# wait dq[15:0] t chvh t vlch t avch t chax t chtv t chtv t chqv t elch t gltx t chqv t chtx t chqx t clk t ch t cl rst# t chtv t chtx t chvl t gltv end of wl q q notes: 1. wait shown as active low (rcr[10] = 0) and asserted with data (rcr[8] = 0). 2. adv# may be held low throughout the synchronous read operation. 3. t avqv, t elqv, and t vlqv apply to legacy-latching only. 4. t acc and t vlvh apply to clock-latching only. 128mb, 256mb, 512mb, 1gb strataflash memory ac read specifications pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 67 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 22: synchronous burst with burst interrupt read (non-mux) t cl a[max:0] clk adv# latency count ce# oe# wait dq[15:0] t chvh t vlch t avch t chax t avch t chax t chtv t chtv t chqv t elch t elch t gltx t chqv t chtx t chqx t clk t ch rst# t chqx t gltv t chvl t chvh t vhvl t vlch t chvl q q q notes: 1. wait shown as active low (rcr[10] = 0) and asserted with data (rcr[8] = 0). 2. a burst can be interrupted by toggling ce# or adv#. 3. for no-wrap bursts, end-of-wordline wait states could occur (not shown in this figure). 4. t avqv, t elqv, and t vlqv apply to legacy-latching only. 5. t acc and t vlvh apply to clock-latching only. 128mb, 256mb, 512mb, 1gb strataflash memory ac read specifications pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 68 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 23: asynchronous single-word read a[max:16] a/dq[15:0] adv# t avav t avqv t avvh t vlvh t vhvl ce# oe# wait t phqv t vlqv t vlvh t vlqv t elvh t glqx t glqx t ehtz t ehtz t eltv t eltv t avav t avqv rst# t elqv t ehqz t elvh t ehel t elqv t oh t oh t ehqz t glqv t ghqz t vhgl t vhgl t ghqz t glqv a a a q q a t vhax t avvh t vhax t phvh notes: 1. wait shown as active low (rcr[10] = 0). 2. back-to-back read operations shown. 3. ce# does not need to toggle between read cycles (i.e., t ehel need not apply). 128mb, 256mb, 512mb, 1gb strataflash memory ac read specifications pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 69 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 24: synchronous 8- or 16-word burst read (a/d mux) a[max:16] clk adv# latency count ce# oe# wait a/dq[15:0] t chvh t avch t chax t chqv t chqv t gltv t elch t chgl t chtv t clk t ch t cl rst# t vlch t gltx t chvl q a a t chqx t chqv q q t chqx t chtv t chtx t ghtv notes: 1. 8-word and 16-word burst are always wrap-only. 2. wait shown as active low (rcr[10] = 0) and asserted with data (rcr[8] = 0). 3. t avqv, t elqv, and t vlqv apply to legacy-latching only. 4. t acc and t vlvh apply to clock-latching only. 128mb, 256mb, 512mb, 1gb strataflash memory ac read specifications pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 70 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 25: synchronous continuous misaligned burst read (a/d mux) a[max:16] clk adv# latency count ce# oe# wait a/dq[15:0] t chvh t avch t chax t chqv t chqv t gltv t elch t chgl t chtv t clk t ch t cl rst# t vlch t gltx t chvl q a a t chqx q end of wl q t chtv t chtx t ghtv t chtv t chtx notes: 1. 8-word and 16-word burst are always wrap-only. 2. wait shown as active low (rcr[10] = 0) and asserted with data (rcr[8] = 0). 3. t avqv, t elqv, and t vlqv apply to legacy-latching only. 4. t acc and t vlvh apply to clock-latching only. figure 26: synchronous burst with burst-interrupt (ad-mux) a[max:16] clk adv# latency count ce# oe# wait a/dq[15:0] t chvh t vlch t avch t chax t chqv t chqv t avch t chax t gltv t elch t chgl t chtv t clk t ch t cl rst# t gltx t chvl t chvh t vlch t chvl q q a a a t chqx a t elch 128mb, 256mb, 512mb, 1gb strataflash memory ac read specifications pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 71 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. notes: 1. t avqv, t elqv, and t vlqv apply to legacy-latching only. 2. t acc and t vlvh apply to clock-latching only. 3. a burst can be interrupted by toggling ce# or adv#. 128mb, 256mb, 512mb, 1gb strataflash memory ac read specifications pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 72 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. ac write specifications table 41: ac write specifications notes 1 and 2 apply to all parameter symbol min max unit notes rst# high recovery to we# low t phwl 150 C ns 3 ce# setup to we# low t elwl 0 C ns 10 we# write pulse width low t wlwh 40 C ns 4 data setup to we# high t dvwh 40 C ns address setup to we# high t avwh 40 C ns ce# hold from we# high t wheh 0 C ns data hold from we# high t whdx 0 C ns address hold from we# high t whax 0 C ns we# pulse width high t whwl 20 C ns 5 v pp setup to we# high t vpwh 200 C ns 3, 7 v pp hold from status read t qvvl 0 C ns 3, 7 wp# hold from status read t qvbl 0 C ns 3, 7 wp# setup to we# high t bhwh 200 C ns 3, 7 we# high to oe# low t whgl 0 C ns 8 adv# low to we# high t vlwh 55 C ns we# high to read valid t whqv t avqv + 30 C ns 3, 6, 9 write operation to asynchronous read transition we# high to address valid t whav write to synchronous read specification we# high to clk high @ 110 mhz t whch 15 C ns 3, 6, 11 we# high to ce# low t whel 9 C ns 3, 6, 11 we# high to adv# low t whvl 7 C ns 3, 6, 11 write specifications with clock active adv# high to we# low t vhwl C 27 ns 11 clk high to we# low t chwl C 27 ns 11 notes: 1. write timing characteristics during erase suspend are the same as write-only opera- tions. 2. a write operation can be terminated with either ce# or we#. 3. sampled, not 100% tested. 4. write pulse width low ( t wlwh or t eleh) is defined from ce# or we# low (whichever occurs last) to ce# or we# high (whichever occurs first). hence, t wlwh = t eleh = t wleh = t elwh. 5. write pulse width high ( t whwl or t ehel) is defined from ce# or we# high (whichever occurs first) to ce# or we# low (whichever occurs last). hence, t whwl = t ehel = t whel = t ehw. 6. t whch must be met when transitioning from a write cycle to a synchronous burst read. in addition ce# or adv# must toggle when we# goes high. 7. v pp and wp# must be at a valid level until erase or program success is determined. 128mb, 256mb, 512mb, 1gb strataflash memory ac write specifications pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 73 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. 8. when performing a read status operation following any command that alters the sta- tus register, t whgl is 20ns. 9. add 10ns if the write operation results in an rcr or block lock status change for the subsequent read operation to reflect this change. 10. either t vhwl or t chwl is required to meet the specification depending on the address latching mechanism; both of these specifications can be ignored if the clock is not tog- gling during the write cycle. 11. if adv# remains low after the write cycle completes, a new read cycle will start. figure 27: write timing a d t wheh t avwh t whdx a[max:16] a/dq[15:0] adv# ce# oe# rst# we# t vhax t avvh t vlvh t vlvh t avvh t elwl t phwl t elwl t whwl t wlwh t vhwl t wlwh t vhax t whax t dvwh t whav t wheh a t whvh d t vlwh 128mb, 256mb, 512mb, 1gb strataflash memory ac write specifications pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 74 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 28: write to write (non-mux) t a vwh t e l wl t e l wl t wheh address adv# ce# we# oe# dq rst# wp# t dvwh t phwl t dvwh t bhwh t whdx t whdx t wheh t a vwh t whax t w l wh t w l wh t whwl t whax figure 29: async read to write (non-mux) address adv# ce# oe# we# wait t vhvl t gltv t ghtz t glqv t oh t dvwh t whdx t ghqz t elqv t avqv t ehqz t ehel t wheh t wlwh t vlwh t elwl a a dq[15:0] q d 128mb, 256mb, 512mb, 1gb strataflash memory ac write specifications pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 75 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 30: write to async read (non-mux) address adv# ce# we# oe# wait t gltv high-z t glqv t ghtz t dvwh t whdx t gltx t elqv t avqv t ghqz t oh t ehqz t ehel t wheh t avwh t whax t wlwh t elwl t whgl write address read address dq d q figure 31: sync read to write (non-mux) address clk ce# adv# oe# wait dq t elch t avch t avwh t chax t chqv t vlvh t vhvl t vlch t chqv t chqx t chqx t whdx t dvwh we# t wlwh t ehel t chtv high-z high-z t chvh t chwl t chvl q0 q1 d 128mb, 256mb, 512mb, 1gb strataflash memory ac write specifications pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 76 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 32: write to sync read (non-mux) a clk adv# ce# we# oe# wait dq t vlch/l t elch/l t whch/l t avch/l t chvh t vhvl t chvl t gltv t chqv t wlwh t whvl t chwl t chtv t whgla t ehel t whel t whwl t chqv t chqx q0 t chqv t chqx q1 t chqx q2 d write adddress read adddress t dvwh t whdx figure 33: write to write (ad-mux) a[max:16] t avwh t avvh t dvwh t whdx t vhax t vlwh t wheh t elwl t elwl t phwl t bhwh t wheh t wlwh tt whwl t wlwh a/dq[15:0][a/d] a d a d adv# ce# we# oe# rst# wp# 128mb, 256mb, 512mb, 1gb strataflash memory ac write specifications pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 77 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 34: async read to write (ad-mux) t vhvl a d a/dq[15:0] adv# ce# oe# we# wait t avvh t avqv t oh t eltv t ehtz t eltv t ehtz t ehel t ehqz t ghqz t glqv t vhgl t elqv t whdx t wlwh t vlwh t dvwh a a[max:16] a a q figure 35: write to async read (ad-mux) t elqv a q a/dq[15:0] ce# adv# we# oe# wait t avwh t whdx t ehel t wheh t ehqz t dvwh t avqv t eltv t ehtz t eltv t ehtz t vlwh t wlwh t elwl t vhvl t ghqz t glqv t whgl t vhgl a a[max:16] a a d 128mb, 256mb, 512mb, 1gb strataflash memory ac write specifications pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 78 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 36: sync read to write (ad-mux) a[max:16] clk ce# adv# oe# wait t elch t avch t avwh t chax t chqv t vlvh t vlch t chqv t chqx t chqx t whdx t vlwh we# t dvwh t ehel t chtv high-z high-z t chvh t chwl t chvl a[15:0] q0 q1 d a a a a figure 37: write to sync read (ad-mux) a[max:16] clk ce# adv# oe# wait t avwh t whch/l t chqv t vlwh t vhvl t chqv t chqv t chqx t chqx we# t ehel t whel t whgl t chwl t wlwh t whvl t chtv t gltv a[15:0] q0 q1 q2 a a a d a t chqx t dvwh t whdx 128mb, 256mb, 512mb, 1gb strataflash memory ac write specifications pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 79 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. electrical specifications C program/erase characteristics table 42: program/erase characteristics note 1 applies to all parameter symbol v ppl or v pph units notes min typ max word programming program time single word (first word) t prog/w C 115 230 s 2 single word (subsequent word) 50 230 buffered programming program time single word t prog/w C 250 500 s one buffer (512 words) 90nm (128C 512mb) t prog/pb C 2.15 4.3 ms 65nm (128C 1024mb) 1.02 2.05 45nm (128C 1024mb) 0.57 1.14 buffer enhanced factory programming (befp) program single word 90nm (128C 512mb) t befp/w C 4.2 C s 3 65nm (128C 1024mb) 2.0 45nm (128C 1024mb) 0.93 befp setup t befp/ setup 5 C C s 3 erasing and suspending erase time 128k-word parameter t ers/mab C 0.9 4 s suspend la- tency program suspend t susp/p C 20 30 s erase suspend t susp/e C 20 30 s blank check main array block main array block t bc/mb C 3.2 C ms notes: 1. typical values measured at t c = 25c and nominal voltages. performance numbers are valid for all speed versions. excludes overhead. sampled, but not 100% tested. 2. conventional word programming: first and subsequent words refer to first word and subsequent words in control mode programming region. 3. averaged over the entire device. befp is not validated at v ppl . 128mb, 256mb, 512mb, 1gb strataflash memory electrical specifications C program/erase characteristics pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 80 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. common flash interface the common flash interface (cfi) is part of an overall specification for multiple com- mand set and control interface descriptions. system software can parse the cfi data- base structure to obtain information about the device, such as block size, density, bus width, and electrical specifications. the system software determines which command set to use to properly perform a write, block erase, or read command, and to oth- erwise control the device. information in the cfi database can be viewed by issuing the read cfi command. read cfi structure output the read cfi command obtains cfi database structure information and always out- puts it on the lower byte, dq[7:0], for a word-wide (x16) flash device. this cfi-compli- ant device always outputs 00h data on the upper byte (dq[15:8]). the numerical offset value is the address relative to the maximum bus width that the device supports, with a starting address of10h, which is a word address for x16 devices. for example, at a starting address of 10h, a read cfi command outputs an ascii q in the lower byte and 00h in the higher byte. in the following tables, address and data are represented in hexadecimal notation. in addition, because the upper byte of word-wide devices is always 00h, the leading 00 has been dropped and only the lower byte value is shown. table 43: example of cfi output (x16 device) as a function of device and mode device hex offset hex code ascii value (dq[15:8]) ascii value (dq[7:0]) address 00010: 51 00 q 00011: 52 00 r 00012: 59 00 y 00013: p_id lo 00 primary vendor id 00014: p_id hi 00 00015: p lo 00 primary vendor table address 00016: p hi 00 00017: a_id lo 00 alternate vendor id 00018: a_id hi 00 : : : : : : : : table 44: cfi database: addresses and sections address section name description 00001:fh reserved reserved for vendor-specific information 00address010h cfi id string command set id (identification) and vendor data offset 0001bh system interface information timing and voltage 00027h device geometry definition layout 128mb, 256mb, 512mb, 1gb strataflash memory common flash interface pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 81 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. table 44: cfi database: addresses and sections (continued) address section name description p primary micron-specific extended query vendor-defined informaton specific to the primary vendor algorithm (offset 15 defines p which points to the primary micron-specific extended query table) cfi id string the cfi id string provides verification that the device supports the cfi specification. it also indicates the specification version and supported vendor-specific command sets. table 45: cfi id string hex offset length description address hex code ascii value (dq[7:0]) 10h 3 query unique ascii string qry 10: - -51 q 11: - -52 r 12: - -59 y 13h 2 primary vendor command set and control interface id code;16-bit id code for vendor- specified algorithms 13: - -00 primary vendor id number 14: - -02 15h 2 extended query table primary algorithm address 15: - -0a primary vendor table ad- dress, primary algorithm 16: - -01 17h 2 alternate vendor command set and control interface id code; 0000h indicates no sec- ond vendor-specified algorithm exists 17: - -00 alternate vendor id number 18: - -00 19h 2 secondary algorithm extended query table address; 0000h indicates none exists 19: - -00 primary vendor table ad- dress, secondary algorithm 1a: - -00 system interface information table 46: system interface information hex offset length description address hex code ascii value (dq[7:0]) 1bh 1 v cc logic supply minimum program/erase voltage bits 0C3 bcd 100mv bits 4C7 bcd volts 1bh - -17 1.7v 1ch 1 v cc logic supply maximum program/erase voltage bits 0C3 bcd 100mv bits 4C 7 bcd volts 1ch - -20 2.0v 1dh 1 v pp [programming] supply minimum program/ erase voltage bits 0C3 bcd 100mv bits 4C7 hex volts 1dh - -85 8.5v 128mb, 256mb, 512mb, 1gb strataflash memory common flash interface pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 82 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. table 46: system interface information (continued) hex offset length description address hex code ascii value (dq[7:0]) 1eh 1 v pp [programming] supply maximum program/ erase voltage bits 0C3 bcd 100mv bits 4C7 hex volts 1eh - -95 9.5v 1fh 1 n such that typical single word program timeout = 2 n s 1fh - -06 64s 20h 1 n such that typical full buffer write timeout = 2 n s 20h - -0b (256, 512 mbit - 90nm; 1024 mbit - 65nm) - -0a (128, 256, 512 mbit - 65nm) 2048s (256, 512 mbit - 90nm; 1024 mbit - 65nm) 1023s (128, 256, 512 mbit - 65nm) 21h 1 n such that typical block erase timeout = 2 n ms 21h - -0a 1s 22h 1 n such that typical full chip erase timeout = 2 n ms 22h - -00 na 23h 1 n such that maximum word program timeout = 2 n times typical 23h - -02 256s 24h 1 n such that maximum buffer write timeout = 2 n times typical 24h - -02 (256, 512 mbit - 90nm; 128, 256, 512 mbit - 65nm) - -01 (1024 mbit - 65nm) 8192s (256, 512 mbit - 90nm; 128, 256, 512 mbit - 65nm) 4096s (1024 mbit - 65nm) 25h 1 n such that maximum block erase timeout = 2 n times typical 25h - -02 4s 26h 1 n such that maximum chip erase timeout = 2 n times typical 26h - -00 na device geometry definition table 47: device geometry hex offset length description address hex code ascii value (dq[7:0]) 27h 1 n such that device size in bytes = 2 n . 27: (page 0 ) 128mb, 256mb, 512mb, 1gb strataflash memory common flash interface pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 83 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. table 47: device geometry (continued) hex offset length description address hex code ascii value (dq[7:0]) 28h 2 flash device interface code assignment: n such that n + 1 specifies the bit field that represents the device width capabilities as described here: bit 0: x8 bit 1: x16 bit 2: x32 bit 3: x64 bits 4C7: C bits 8C15: C 28: - -01 x16 29: - -00 2ah 2 n such that maximum number of bytes in write buffer = 2 n 2ah - -0a 1024 2bh - -00 2ch 1 number of erase block regions (x) within the device: x = 0 indicates no erase blocking; the device erases in bulk x specifies the number of device regions with one or more contiguous, same-size erase blocks symmetrically blocked partitions have one blocking re- gion 2ch (page 0 ) 2dh 4 erase block region 1 information: bits 0C15 = y, y + 1 = number of identical-size erase blocks bits 16C31 = z, region erase block(s) size are z x 256 bytes 2d: 30: (page 0 ) 31h 4 erase block region 2 information: bits 0C15 = y, y + 1 = number of identical-size erase blocks bits 16C31 = z, region erase block(s) size are z x 256 bytes 31: 34: (page 0 ) 35h 4 reserved for future erase block region information 35: 38: (page 0 ) note: 1. see the bit field table. table 48: block region map information address 128mb 256mb 512mb 1gb bottom top bottom top bottom top bottom top 27: - -18 - - - -19 - - - -1a - - - -1b - - 28: - -01 - - - -01 - - - -01 - - - -01 - - 29: - -00 - - - -00 - - - -00 - - - -00 - - 2a: - -0a - - - -0a - - - -0a - - - -0a - - 2b: - -00 - - - -00 - - - -00 - - - -00 - - 2c: - -01 - - - -01 - - - -01 - - - -01 - - 128mb, 256mb, 512mb, 1gb strataflash memory common flash interface pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 84 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. table 48: block region map information (continued) address 128mb 256mb 512mb 1gb bottom top bottom top bottom top bottom top 2d: - -ff - - - -7f - - - -ff - - - -ff - - 2e: - -00 - - - -00 - - - -00 - - - -01 - - 2f: - -00 - - - -00 - - - -00 - - - -00 - - 30: - -04 - - - -04 - - - -04 - - - -04 - - 128mb, 256mb, 512mb, 1gb strataflash memory common flash interface pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 85 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. primary micron-specific extended query table 49: primary micron-specific extended query hex offset p = 10ah length description address hex code ascii value (dq[7:0]) (p+0)h (p+1)h (p+2)h 3 primary extended query table, unique ascii string: pri 10a: - -50 p 10b: - -52 r 10c: - -49 i (p+3)h 1 major version number, ascii 10d: - -31 1 (p+4)h 1 minor version number, ascii 10e: - -34 4 (p+5)h (p+6)h (p+7)h (p+8)h 4 optional feature and command support (1 = yes; 0 = no) bits 10C31 are reserved; undefined bits are 0 if bit 31 = 1, then another 31-bit field of optional features follows at the end of the bit 30 field 10f: - -e6 (non- mux) - -66 (a/d mux) C 110: - -07 (90nm, 65nm) C 111: - -00 C 112: - -00 C bit 0: chip erase supported bit 0 = 0 no bit 1: suspend erase supported bit 1 = 1 yes bit 2: suspend program supported bit 2 = 1 yes bit 3: legacy lock/unlock supported bit 3 = 0 no bit 4: queued erase supported bit 4 = 0 no bit 5: instant individual block locking supported bit 5 = 1 yes bit 6: otp bits supported bit 6 = 1 yes bit 7: page mode read supported bit 7 = 0 no: a/d mux yes: non-mux bit 8: synchronous read supported bit 8 = 1 yes bit 9: simultaneous operations supported bit 9 = 1 yes bit 10: reserved bit 10 = 0 no bit 30: cfi links to follow bit 30 = 0 no bit 31: another optional features field to follow. bit 31 = 0 no (p+9)h 1 supported functions after suspend: read array, status, query other supported options: bits 1C7 reserved; undefined bits are 0 113: - -01 C bit 0: program supported after erase suspend bit 0 = 1 yes (p+a)h (p+b)h 2 block status register mask: bits 2 C 3 and 6 - 15 are reserved; undefined bits are 0 114: - -33 (90nm, 65nm) C 115: C bit 0: block lock bit status register active bit 0 = 1 yes bit 1: block lock-down bit status active bit 1 = 1 yes 128mb, 256mb, 512mb, 1gb strataflash memory common flash interface pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 86 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. table 49: primary micron-specific extended query (continued) hex offset p = 10ah length description address hex code ascii value (dq[7:0]) (p+c)h 1 v cc logic supply highest performance program/ erase voltage bits 0C3 bcd 100mv bits 4C7 bcd value in volts 116: - -18 1.8v (p+d)h 1 v pp optimum program/erase voltage bits 0C3 bcd 100mv bits 4C7 hex value in volts 117: - -90 9.0v table 50: one time programmable (otp) space information hex offset p = 10ah length description address hex code ascii value (dq[7:0]) (p+e)h 1 number of otp block fields in jedec id space. 00h indicates that 256 otp fields are available 118: - -02 2 (p+f)h (p+10)h (p+11)h (p+12)h 4 otp field 1: this field describes user-available otp bytes. some are preprogrammed with device-unique se- rial numbers. others are user-programmable. bits 0C15 point to the otp lock byte (the first byte). the following bytes are factory preprogrammed and user-programmable: bits 0C7 = lock/bytes jedec plane physical low ad- dress. bits 8C15 = lock/bytes jedec plane physical high address. bits 16C23 = n where 2 n equals factory-preprog- rammed bytes. bits 24C31 = n where 2 n equals user-programma- ble bytes. 119: - -80 80h 11a: - -00 00h 1b: - -03 8 byte 11c: - -03 8 byte (p+13)h (p+14)h (p+15)h (p+16)h 4 protection field 2: bits 0C31 point to the protection register physical lock word address in the jedec plane. the bytes that follow are factory or user-progam- mable. 11d: - -89 89h 11e: - -00 00h 11f: - -00 00h 120: - -00 00h (p+17)h (p+18)h (p+19)h 3 bits 32C39 = n where n equals factory-program- med groups (low byte). bits 40C47 = n where n equals factory program- med groups (high byte). bits 48C55 = n where 2n equals factory-program- med bytes/groups. 121: - -00 0 122: - -00 0 123: - -00 0 128mb, 256mb, 512mb, 1gb strataflash memory common flash interface pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 87 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. table 50: one time programmable (otp) space information (continued) hex offset p = 10ah length description address hex code ascii value (dq[7:0]) (p+1a)h (p+1b)h (p+1c)h 3 bits 56C63 = n where n equals user-programmed groups (low byte). bits 64C71 = n where n equals user-programmed groups (high byte). bits 72C79 = n where n equals user programma- ble bytes/groups. 124: - -10 16 125: - -00 0 126: - -04 16 table 51: burst read informaton hex offset p = 10ah length description address hex code ascii value (dq[7:0]) (p+1d)h 1 page mode read capability: bits 7C0 = n where 2 n hex value represents the number of read page bytes. see offset 28h for device word width to determine page mode data output width. 00h indicates no read page buffer. 127: - -05 (non mux) - -00 (a/d mux) 32 byte (non mux) 0 (a/d mux) (p+1e)h 1 number of synchronous mode read configuration fields that follow. 00h indicates no burst capabili- ty. 128: - -03 3 (p+1f)h 1 synchronous mode read capability configuration 1: bits 3C7 = reserved. bits 0C2 = n where 2 n+1 hex value represents the maximum number of continuous synchronous reads when the device is configured for its maxi- mum word width. a value of 07h indicates that the device is capa- ble of continuous linear bursts that will output data until the internal burst counter reaches the end of the devices burstable address space. this fieldss 3-bit value can be written directly to the rcr bits 0C2 if the device is configured for its maximum word width. see offset 28h for word width to determine the burst data output width. 129: - -02 8 (p+20)h 1 synchronous mode read capability configuration 2. 12a: - -03 16 (p+21)h 1 synchronous mode read capability configuration 3. 12b: - -07 cont 128mb, 256mb, 512mb, 1gb strataflash memory common flash interface pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 88 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. table 52: partition and block erase region information hex offset p = 10ah description optional features and commands length address bottom top bottom top (p+22)h (p+22)h number of device hardware partition regions within the device: x = 0: a single hardware partition device (no fields follow). x specifies the number of device partition regions containing one or more contiguous erase block regions 1 12c: 12c: table 53: partition region 1 information: top and bottom offset/address hex offset p = 10ah description optional features and commands length address bottom top bottom top (p+23)h (p+23)h data size of this partition region information field: (number of addressable locations, including this field). 2 12d: 12d: (p+24)h (p+24)h 12e: 12e: (p+25)h (p+26)h (p+25)h (p+26)h number of identical partitions within the partition region. 2 12f: 12f: 130: 130: (p+27)h (p+27)h number of program or erase operations allowed in a partition: bits 0C3 = number of simultaneous program opera- tions. bits 4C7 = number of simultaneous erase operations. 1 131: 131: (p+28)h (p+28)h simultaneous program or erase operations al- lowed in other partitions while a partition in this re- gion is in program mode: bits 0C3 = number of simultaneous program opera- tions. bits 4C7 = number of simultaneous erase operations. 1 132: 132: (p+29)h (p+29)h simultaneous program or erase operations al- lowed in other partitions while a partition in this re- gion is in erase mode: bits 0C3 = number of simultaneous program opera- tions. bits 4C7 = number of simultaneous erase operations. 1 133: 133: 128mb, 256mb, 512mb, 1gb strataflash memory common flash interface pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 89 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. table 53: partition region 1 information: top and bottom offset/address (continued) hex offset p = 10ah description optional features and commands length address bottom top bottom top (p+2a)h (p+2a)h types of erase block regions in this partition region: x = 0: no erase blocking; the partition region erases in bulk. x = number of erase block regions with contiguous, same-size erase blocks. symmetrically blocked partitions have one blocking region. partition size = (type 1 blocks) x (type 1 block sizes) + (type 2 blocks) x (type 2 block sizes) +...+ (type n blocks) x (type n block sizes). 1 134: 134: (p+2b)h (p+2c)h (p+2d)h (p+2e)h (p+2b)h (p+2c)h (p+2d)h (p+2e)h partition region 1 (erase block type 1) information: bits 0C15 = y, y+1 = number of identical-sized erase blocks in a partition. bits 16C31 = z, where region erase block(s) size is z x 256 bytes. 4 135: 135: 136: 136: 137: 137: 138: 138: (p+2f)h (p+30)h (p+2f)h (p+30)h partition 1 (erase block type 1): minimum block erase cycles x 1000 2 139: 139: 13a: 13a: (p+31)h (p+31)h partition 1 (erase block type 1) bits per cell; internal edac: bits 0C3 = bits per cell in erase region bit 4 = internal edac used (1 = yes, 0 = no) bits 5C7 = reserved for future use 1 13b: 13b: (p+32)h (p+32)h partition 1 (erase block type 1) page mode and syn- chronous mode capabilities: bits 0 = page mode host reads permitted (1 = yes, 0 = no) bit 1 = synchronous host reads permitted (1 = yes, 0 = no) bit 2 = synchronous host writes permitted (1 = yes, 0 = no) bits 3C7 = reserved for future use 1 13c: 13c: (p+33)h (p+33)h partition 1 (erase block type 1) programming region information: bits 0 - 7 = x, 2 x : programming region aligned size (bytes) bits 8 - 14 = reserved for future use bit 15 = legacy flash operation; ignore 0:7 bit 16 - 23 = y: control mode valid size (bytes) bit 24 - 31 = reserved for future use bit 32 - 39 = z: control mode invalid size (bytes) bit 40 - 46 = reserved for future use bit 47 = legacy flash operation (ignore 23:16 and 39:32) 6 13d: 13d: (p+34)h (p+34)h 13e: 13e: (p+35)h (p+35)h 13f: 13f: (p+36)h (p+36)h 140: 140: (p+37)h (p+37)h 141: 141: (p+38)h (p+38)h 142: 142: 128mb, 256mb, 512mb, 1gb strataflash memory common flash interface pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 90 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. table 54: partition and erase block map information address 128mb 256mb 512mb 1gb bottom top bottom top bottom top bottom top 12c: - -01 - - - -01 - - - -01 - - - -01 - - 12d: - -16 - - - -16 - - - -16 - - - -16 - - 12e: - -00 - - - -00 - - - -00 - - - -00 - - 12f: - -08 - - - -08 - - - -08 - - - -08 - - 130: - -00 - - - -00 - - - -00 - - - -00 - - 131: - -11 - - - -11 - - - -11 - - - -11 - - 132: - -00 - - - -00 - - - -00 - - - -00 - - 133: - -00 - - - -00 - - - -00 - - - -00 - - 134: - -01 - - - -01 - - - -01 - - - -01 - - 135: - -07 - - - -0f - - - -1f - - - -3f - - 136: - -00 - - - -00 - - - -00 - - - -00 - - 137: - -00 - - - -00 - - - -00 - - - -00 - - 138: - -04 - - - -04 - - - -04 - - - -04 - - 139: - -64 - - - -64 - - - -64 - - - -64 - - 13a: - -00 - - - -00 - - - -00 - - - -00 - - 13b: - -12 - - - -12 - - - -12 - - - -12 - - 13c: - -02 mux - -03 non mux - - - -02 mux - -03 non mux - - - -02 mux - -03 non mux - - - -02 mux - -03 non mux - - 13d: - -0a - - - -0a - - - -0a - - - -0a - - 13e: - -00 - - - -00 - - - -00 - - - -00 - - 13f: - -10 - - - -10 - - - -10 - - - -10 - - 140: - -00 - - - -00 - - - -00 - - - -00 - - 141: - -10 - - - -10 - - - -10 - - - -10 - - 142: - -00 - - - -00 - - - -00 - - - -00 - - 128mb, 256mb, 512mb, 1gb strataflash memory common flash interface pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 91 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. flowcharts figure 38: word program procedure 0 program complete 1 sr7 = write 0x41, word address start write data, word address (setup) (confirm) read status register program suspend loop yes no suspend full status check (if desired) bus operation command comments write program setup data = 0x41 address = location to program write data data = data to program address = location to program read none status register data idle none check sr7 1 = write state machine ready 0 = write state machine busy notes: 1. repeat for subsequent word program operations. 2. full status register check can be done after each program or after a sequence of pro- gram operations. 3. write 0xff after the last operation to set to the read array state. 128mb, 256mb, 512mb, 1gb strataflash memory flowcharts pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 92 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 39: word program full status check procedure program successful 1 0 1 0 1 0 read status register sr3 = sr4 = sr1 = program error device protect error v pp range error note: sr3 must be cleared before the write state machine will support further program attempts. bus operation command comments idle none check sr3 1 = v pp error idle none check sr4 1 = data program error idle none check sr1 1 = block locked; operation aborted note: 2. if an error is detected, clear the status register before continuing operations. only the clear staus register command clears the status register error bits. 128mb, 256mb, 512mb, 1gb strataflash memory flowcharts pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 93 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 40: program suspend/resume procedure 0 1 sr7 = write b0h any address start write 70h same partition program suspend read status write ffh suspend partition read array program resume read status write d0h any address write 70h same partition read array data write ffh programmed partition read array read array data read status register 0 1 sr2 = program resumed no yes done reading? program completed 128mb, 256mb, 512mb, 1gb strataflash memory flowcharts pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 94 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. bus operation command comments write program suspend data = b0h address = block to suspend write read status data = 70h address = same partition read status register data address = suspended block standby check sr7 1 = write state machine ready 0 = write state machine busy standby check sr2 1 = program suspended 0 = program completed write read array data = ffh address = any address within the suspended partition read read array data from block other than the one being pro- grammed write program resume data = d0h address = suspended block if the suspended partition was placed in read array mode: write read status return partition to status mode: data = 70h address = same partition 128mb, 256mb, 512mb, 1gb strataflash memory flowcharts pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 95 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 41: buffer programming procedure no yes x = 0? word address in different block? word address in different block? write 0xe9, base colony address start write word count-1, base colony address; (x = word count) (setup) (bp load 1) write data, word address (bp load 2) write data, word address (confirm) x = x - 1 yes no yes yes no no data ? 0xd0? buffered program abort read data (sr data), block address full status register check (if desired) buffered program complete 0 1 sr7 = ? 128mb, 256mb, 512mb, 1gb strataflash memory flowcharts pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 96 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. bus operation command comments write buffered program setup data = 0xe9 addr = colony base address write buffered program load 1 data = word count -1 1 address = block address write 2, 3 buffered program load 2 data = data to be programmed address = word address write 4, 5 buffered program confirm data = 0xd0 address = address within block read none status register data address = block address notes: 1. d[8:0] is loaded as word count-1. 2. repeat buffered program load 2 until the word count is achieved. (load up to 512 words.) 3. the command sequence aborts if the address of the buffered program load 2 cycle is in a different block from the address of the buffered program setup cycle. 4. the command sequence aborts if the address of the buffered program confirm cy- cle is in a different block from the address of the buffered program setup cycle. al- so, an abort will occur if the data of the buffered program confirm cycle data is not 0xd0. 5. the read mode changes to status read on the buffered program confirm command. 128mb, 256mb, 512mb, 1gb strataflash memory flowcharts pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 97 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 42: buffered enhanced factory programming (befp) procedure no (sr7 = 1) yes (sr7 = 0) yes (sr0 = 0) befp setup successful? v pp applied, block unlocked start exit write 0x80 @ 1 st word address write 0xd0 @ 1 st word address befp setup delay read status register check v pp , lock errrors (sr3,1) yes no x = 512? initialize count: x = 0 data stream ready write data @ 1 st word address increment count: x = x + 1 read status register program done? yes no last data? write 0xffff, address in different block within partition setup phase program and verify phase exit phase program complete yes (sr7 = 1) no (sr7 = 0) befp exited? read status register full status check procedure no (sr0 = 1) bus operation action comments setup phase write unlock block v pph applied to v pp write befp setup data = 0x80 @ first word address 1 write befp confirm data = 0xd0 @ first word address read status register data = status register data adress = first word address 128mb, 256mb, 512mb, 1gb strataflash memory flowcharts pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 98 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. bus operation action comments standby befp setup done? check sr7: 0 = befp ready 1 = befp not ready standby error condi- tion check if sr7 is set, check: sr3 set = v pp error sr1 set = locked block program and verify phase read status register data = status register data address = first word address standby data stream ready? check sr0: 0 = ready for data 1 = not ready for data standby initialize count x = 0 write load buffer data = data to program address = first word address 2 standby increment count x = x + 1 standby buffer full? x = 512? yes = read sr0 no = load next data word read status register data = status register data address = first word address standby program done? check sr0: 0 = program done 1 = program in progress standby last data? no = fill buffer again yes = exit write exit program and verify phase data = 0xffff @ address not in current block exit phase read status register data = status register data address = first word address standby check exit sta- tus check sr7: 0 = exit not completed 1 = exit completed notes: 1. repeat for subsequent blocks. 2. after befp exit, a full status register check can determine if any program error occurred. 3. see the word program full status register check procedure flowchart. 4. write 0xff to enter read array state. 128mb, 256mb, 512mb, 1gb strataflash memory flowcharts pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 99 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 43: block erase procedure 0 block erase complete 1 sr7 = write 0x20, block address start write 0xd0, block address (block erase) (erase confirm) read status register suspend erase loop yes no suspend erase? full erase status check (if desired) bus operation command comments write block erase setup data = 0x20 address = block to be erased write erase con- firm data = 0xd0 address = block to be erased read none status register data idle none check sr7 1 = write state machine ready 0 = write state machine busy notes: 1. repeat for subsequent block erasures. 2. full status register check can be done after each block erase or after a sequence of block erasures. 3. write 0xff after the last operation to enter read array mode. 128mb, 256mb, 512mb, 1gb strataflash memory flowcharts pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 100 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 44: block erase full status check procedure block erase successful 1 0 1, 1 0 1 0 read status register sr3 = sr4, 5 = sr1 = command sequence error 1 0 sr5 = block erase error block locked error v pp range error bus operation command comments idle none check sr3 1 = v pp range error idle none check sr[4, 5] both 1 = command sequence error idle none check sr5 1 = block erase error idle none check sr1 1 = attempted erase of locked block; erase aborted notes: 1. only the clear staus register command clears the sr[1, 3, 4, 5]. 2. if an error is detected, clear the status register before attempting an erase retry or other error recovery. 128mb, 256mb, 512mb, 1gb strataflash memory flowcharts pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 101 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 45: erase suspend/resume procedure 0 1 sr7 = write 0x70, same partition start write 0xb0, any address (erase suspend) (read status) program read (erase resume) (read status) write 0xd0, any address program loop read array data write 0x70, same partition write 0xff, erased partition (read array) read array data read status register 0 1 sr6 = erase resumed no done read or program? erase completed 128mb, 256mb, 512mb, 1gb strataflash memory flowcharts pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 102 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. bus operation command comments write read status data = 0x70 address = any partition address write erase sus- pend data = 0xb0 address = same partition address as above read none status register data address = same partition idle none check sr7 1 = write state machine ready 0 = write state machine busy idle none check sr6 1 = erase suspended 0 = erase completed write any read or program data = command for desired operation address = any address within the suspended partition read or write none read array or program data from/to block other than the one being erased write program re- sume data = 0xd0 address = any address if the suspended partition was placed in read array mode or a program loop: write read status register return partition to status mode: data = 0x70 address = same partition 128mb, 256mb, 512mb, 1gb strataflash memory flowcharts pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 103 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 46: block lock operations procedure no yes locking change? write 0x60, block address start write either 0x01/0xd0/0x2f, block address (lock confirm) (read device id) (lock setup) (read array) optional write 0xff partition address write 0x90 read block lock status lock change complete bus operation command comments write lock setup data = 0x60 address = block to lock/unlock/lock-down write lock, un- lock, or lock-down confirm data = 0x01 (block lock) data = 0xd0 (block unlock) data = 0x2f (lock-down block) address = block to lock/unlock/lock-down write (op- tional) read device id data = 0x90 address = block address + offset 2 read (option- al) block lock status block lock status data address = block address + offset 2 idle none confirm locking change on d[1, 0] write read array data = 0xff address = block address 128mb, 256mb, 512mb, 1gb strataflash memory flowcharts pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 104 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 47: protection register programming procedure 0 program complete 1 sr7 = write 0xc0, pr address start write pr address and data (program setup) (confirm data) read status register full status check (if desired) bus operation command comments write program pr setup data = 0xc0 address = first location to program write protection program data = data to program address = location to program read none status register data idle none check sr7 1 = write state machine ready 0 = write state machine busy notes: 1. program protection register operation addresses must be within the protection register address space. addresses outside this space will return an error. 2. repeat for subsequent program operations. 3. full status register check can be done after each program operation or after a se- quence of program operations. 4. write 0xff after the last operation to set to the read array state. 128mb, 256mb, 512mb, 1gb strataflash memory flowcharts pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 105 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 48: protection register programming full status check procedure program successful 1 0 1 0 1 0 read status register data sr3 = sr4 = sr1 = program error register locked; program aborted v pp range error bus operation command comments idle none check sr3 1 = v pp error idle none check sr4 1 = programming error idle none check sr1 1 = register locked; operation aborted notes: 1. only the clear staus register command clears sr[1, 3, 4]. 2. if an error is detected, clear the status register before attempting a program retry or other error recovery. 128mb, 256mb, 512mb, 1gb strataflash memory flowcharts pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 106 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 49: blank check procedure 0 no blank check 1 sr7 = write 0xbc, block address start write 0xd0, block address read status register full blank check status read bus operation command comments write blank check setup data = 0xbc address = block to be read write blank check confirm data = 0xd0 address = block to be read read none status register data idle none check sr7 1 = write state machine ready 0 = write state machine busy notes: 1. repeat for subsequent block blank check. 2. full status register check should be read after blank check has been performed on each block. 128mb, 256mb, 512mb, 1gb strataflash memory flowcharts pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 107 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 50: blank check full status check procedure blank check successful 1, 1 0 1 0 read status register sr[4:5] = sr[5] = blank check error command sequence error bus operation command comments idle none check sr[4, 5] 1 = command sequence error idle none check sr5 1 = blank check error notes: 1. sr[1, 3] must be cleared before the write state machine will allow blank check to be per- formed. 2. only the clear staus register command clears sr[1, 3, 4, 5]. 3. if an error is detected, clear the status register before attempting a blank check retry or other error recovery. 128mb, 256mb, 512mb, 1gb strataflash memory flowcharts pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 108 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. aadm mode aadm feature overview the following is a list of general requirements for aadm mode. feature availability. aadm mode is available in devices that are configured as a/d mux. with this configuration, aadm mode is enabled by setting a specific volatile bit in the read configuration register. high-address capture (a[max:17]). when aadm mode is enabled, a[max:17] and a[16:1] are captured from the a/ dq[15:0] balls. the selection of a[max:17] or a[16:1] is determined by the state of the oe# input, as a[max:17] is captured when oe# is at v il . read and write cycle support. in aadm mode, both asynchronous and synchronous cycles are supported. customer requirements. for aadm operation, the customer is required to ground a[max:17]. other characteristics. for aadm, all other device characteristics (program time, erase time, i ccs , etc.) are the same as a/d mux unless otherwise stated. aadm mode enable (rcr[4] = 1) setting rcr[4] to its non-default state (1b) enables aadm mode. the default device configuration upon reset or power-up is a/d mux mode. upon setting rcr[4] = 1, the upper addresses, a[max:17] are latched. all 0s are latched by default. bus cycles and address capture aadm bus operations have one or two address cycles. for two address cycles, the upper address (a[max:17]) must be issued first, followed by the lower address (a[16:1]). for bus operations with only one address cycle, only the lower address is issued. the upper address that applies is the one that was most recently latched on a previous bus cycle. for all read cycles, sensing begins when the lower address is latched, regardless of whether there are one or two address cycles. in bus cycles, the external signal that distinguishes the upper address from the lower address is oe#. when oe# is at v ih , a lower address is captured; when oe# is at v il , an upper address is captured. when the bus cycle has only one address cycle, the timing waveform is similar to a/d mux mode. the lower address is latched when oe# is at v ih , and data is subsequently outputted after the falling edge of oe#. when the device initially enters aadm mode, the upper address is internally latched as all 0s. wait behavior the wait behavior in aadm mode functions the same as the legacy non-mux wait behavior (a/d mux wait behavior is unique). in other words, wait will always be driven whenever dq[15:0] is driven, and wait will tri-state whenever dq[15:0] tri-state. 128mb, 256mb, 512mb, 1gb strataflash memory aadm mode pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 109 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. in asynchronous mode (rcr[15] = 1b), wait always indicates valid data when driven. in synchronous mode (rcr[15] = 0b), wait indicates valid data only after the latency count has lapsed and the data output data is truly valid. asynchronous read and write cycles for asynchronous read and write cycles, adv# must be toggled high-low-high a minimum of one time and a maximum of two times during a bus cycle. if adv# is tog- gled low twice during a bus cycle, oe# must be held low for the first adv# rising edge and oe# must be held high for the second adv# rising edge. the first adv# rising edge (with oe# low) captures a[max:16]. the second adv# rising edge (with oe# high) captures a[16:1]. each bus cycle must toggle adv# high-low-high at least one time in order to capture a[16:1]. for asynchronous reads, sensing begins when the lower ad- dress is latched. during asynchronous cycles, it is optional to capture a[max:17]. if these addresses are not captured, then the previously captured a[max:17] contents will be used. asynchronous read cycles for aadm, note that asynchronous read access is from the rising edge of adv# rather than the falling edge ( t vhqv rather than t vlqv). table 55: aadm asynchronous and latching timings symbol min (ns) max (ns) notes t glqv 20 t phqv 150 t elqx 0 t glqx 0 t ehqz 9 t ghqz 9 t oh 0 t ehel 7 t eltv 11 t ehtz 9 t gltv 7 t gltx 0 t ghtz 9 t avvh 5 t elvh 9 t vlvh 7 t vhvl 7 t vhax 5 t vhgl 3 t vhqv 96 1 t phvh 30 128mb, 256mb, 512mb, 1gb strataflash memory aadm mode pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 110 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. table 55: aadm asynchronous and latching timings (continued) symbol min (ns) max (ns) notes t ghvh 3 t glvh 3 t vhgh 3 notes: 1. a read cycle may be restarted prior to completing a pending read operation, but this may occur only once before the sense operation is allowed to complete. 2. t vhqv applies to asynchronous read access time. figure 51: aadm asynchronous read cycle (latching a[max:0]) a/dq[15:0] adv# ce# oe# wait t vlvh t vhvl t avvh t avvh t vhax t elvh t gltv t glvh t vhgh t ghvh t vhgl t ghtz t ehtz t ghqz t ghvh + t vhgl t glqx t glqv t ehqz t ehel t vlvh t vhqv t vhax t gltx a[max:16] a[15:0] dq[15:0] notes: 1. ce# need not be de-asserted at beginning of the cycle if oe# does not have output con- trol. 2. diagram shows wait as active low (rcr[10] = 0). figure 52: aadm asynchronous read cycle (latching a[15:0] only) a/dq[15:0] adv# ce# oe# wait t avvh t vhax t elvh t gltv t vhgl t ghtz t ehtz t ghqz t vhgh + t ghvl t glqx t glqv t ehqz t ehel t vlvh t vhqv t gltx a[15:0] dq[15:0] notes: 1. diagram shows wait as active low (rcr[10] = 0). 128mb, 256mb, 512mb, 1gb strataflash memory aadm mode pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 111 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. 2. without latching a[max:17] in the asynchronous read cycle, the previously latched a[max:17] applies. asynchronous write cycles table 56: aadm asynchronous write timings symbol min (ns) t phwl 150 t elwl 0 t wlwh 40 t dvwh 40 t wheh 0 t whdx 0 t whwl 20 t vpwh 200 t wvvl 0 t bhwh 200 t whgl 0 t ghwl 0 notes: 1. a read cycle may be restarted prior to completing a pending read operation, but this may occur only once before the sense operation is allowed to complete. 2. t vhqv applies to asynchronous read access time. figure 53: aadm asynchronous write cycle (latching a[max:0]) a/dq[15:0] adv# ce# oe# t whwl t dvwh t whgl t wlwh t bhwh t ghwl t elwl t whdx t elwl t wheh we# wp# rst# t phwl a[max:16] a[15:0] dq[15:0] note: 1. ce# need not be de-asserted at beginning of cycle if oe# does not have output control. 128mb, 256mb, 512mb, 1gb strataflash memory aadm mode pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 112 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 54: aadm asynchronous write cycle (latching a[15:0] only) a/dq[15:0] adv# ce# oe# t whwl t dvwh t whgl t wlwh t bhwh t elwl t whdx t elwl t wheh we# wp# rst# t phwl a[15:0] dq[15:0] note: 1. without latching a[max:16] in the write cycle, the previously latched a[max:16] ap- plies. synchronous read and write cycles just as asynchronous bus cycles, synchronous bus cycles (rcr[15] = 0b) can have one or two address cycles. if the are two address cycles, the upper address must be latched first with oe# at v il followed by the lower address with oe# at v ih . if there is only one ad- dress cycle, only the lower address will be latched and the previously latched upper ad- dress applies. for reads, sensing begins when the lower address is latched, but for syn- chronous reads, addresses are latched on a rising clock clk instead of a rising adv# edge. for synchronous bus cycles with two address cycles, it is not necessary to de-assert adv# between the two address cycles. this allows both the upper and lower address to be latched in only two clock periods. synchronous read cycles for synchronous read operation, the specifications in the aadm asynchronous and latching timings table also apply. table 57: aadm synchronous timings symbol target (104 mhz) min (ns) target (104 mhz) max (ns) notes t clk 9 t rise/ t fall 1.5 6 t avch 3 t vlch 3 t elch 3.5 t chqv 7 t chqx 2 t chax 5 5 128mb, 256mb, 512mb, 1gb strataflash memory aadm mode pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 113 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. table 57: aadm synchronous timings (continued) symbol target (104 mhz) min (ns) target (104 mhz) max (ns) notes t chtv 7 t chvl 2.5 t chtx 2 t chvh 2 t chgl 2.5 4, 5 t vlvh t clk 2 t clk 3, 4 t vhch 3 t chgh 2 t ghch 2 t glch 3 notes: 1. in synchronous burst read cycles, the asynchronous oe# to adv# setup and hold times must also be met ( t ghvh and t vhgl) to signify that the address capture phase of the bus cycle is complete. 2. a read cycle may only be terminated (prior to the completion of sensing data) one time before a full bus cycle must be allowed to complete. 3. the device must operate down to 9.6 mhz in synchronous burst mode. 4. during the address capture phase of a read burst bus cycle, oe# timings relative to clk shall be identical to those of adv# relative to clk. 5. to prevent a/d bus contention between the host and the memory device, oe# may only be asserted low after the host has satisfied the addr hold spec, t chax. 6. rise and fall time specified between v il and v ih . figure 55: aadm synchronous burst read cycle (adv# de-asserted between address cycles) a/dq[15:0] adv# ce# oe# we# wait t chvl t vlch t avch t avch t chax t chqx t elch t gltv t chtv t glch t chgh t ghch t chgl t chtx t chqv t chax t gltx a[max:16] a a[15:0] dq[15:0] dq[15:0] clk t chvh t chvl t vlch t chvh latency count notes: 1. ce# need not be de-asserted at beginning of cycle if oe# does not have output control. 2. diagram shows wait as active low (rcr[10] = 0) and asserted with data (rcr[8] = 0). 3. for no-wrap bursts, end-of-wordline wait states could occur (not shown). 128mb, 256mb, 512mb, 1gb strataflash memory aadm mode pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 114 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 56: aadm synchronous burst read cycle (adv# not de-asserted between address cycles) a/dq[15:0] adv# ce# oe# we# wait t chvl t vlch t avch t avch t chax t chqx t elch t gltv t chtv t glch t chgh t ghch t chgl t chtx t chqv t chax t gltx a[max:16] a a[15:0] dq[15:0] dq[15:0] clk t chvh latency count notes: 1. ce# need not be de-asserted at beginning of cycle if oe# does not have output control. 2. diagram shows wait as active low (rcr[10] = 0) and asserted with data (rcr[8] = 0). 3. for no-wrap bursts, end-of-wordline wait states could occur (not shown). figure 57: aadm synchronous burst read cycle (latching a[15:0] only) a/dq[15:0] adv# ce# oe# we# wait t chvl t vlch t avch t chax t chqx t elch t gltv t chtv t chgl t chtx t chqv t gltx a a[15:0] dq[15:0] dq[15:0] clk t chvh latency count notes: 1. diagram shows wait as active low (rcr[10] = 0) and asserted with data (rcr[8] = 0). 2. for no-wrap bursts, end-of-wordline wait states could occur (not shown). 3. without latching a[max:16] in the synchronous read cycle, the previously latched a[max:16] applies. 128mb, 256mb, 512mb, 1gb strataflash memory aadm mode pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 115 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. synchronous write cycles for synchronous writes, only the address latching cycle(s) are synchronous. synchro- nous address latching is depicted in the synchronous read cycles. the actual write operation (rising we# edge) is asynchronous and is independent of clk. asynchronous writes are depicted in asynchronous write cycles. system boot systems that use the aadm mode will boot from the bottom 128kb of device memory because a[max:17] are expected to be grounded in-system. the 128kb boot region is sufficient to perform required boot activities before setting rcr[4] to enable aadm mode. 128mb, 256mb, 512mb, 1gb strataflash memory aadm mode pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 116 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. ordering information figure 58: part number chart for g18 components pc 28f 512 g 18 f f package designator pc = easy bga, rohs product line designator 28f = micron flash memory voltage 18 = 1.8 core and i/o interface f = non-mux a = ad-mux shipping media e = tray f = tape and reel device density configuration 512 = 512mb, x16 256 = 256mb, x16 128 = 128mb, x16 00a = 1gb, x16 nor flash product family g = strataflash embedded memory table 58: valid line items part number density package interface shipping media pc28f128g18fe 128mb easy bga non-mux tray pc28f128g18ff 128mb easy bga non-mux tape and reel pc28f256g18fe 256mb easy bga non-mux tray pc28f256g18ff 256mb easy bga non-mux tape and reel pc28f256g18ae 256mb easy bga ad-mux tray PC28F256G18AF 256mb easy bga ad-mux tape and reel pc28f512g18fe 512mb easy bga non-mux tray pc28f512g18ff 512mb easy bga non-mux tape and reel pc28f00ag18fe 1gb easy bga non-mux tray pc28f00ag18ff 1gb easy bga non-mux tape and reel 128mb, 256mb, 512mb, 1gb strataflash memory ordering information pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 117 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. revision history rev. f C 8/11 ? removed (45nm, 65nm, litho) from the device id codes table. ? changed balls h2 and h6 from v ss to v ssq in figure 2. ? corrected a/d mux symbol from a[max:16] to a[max:17] in the signal descriptions table. ? added the address mapping for address/ data mux mode table. ? updated the read configuration register bit definitions table. rev. e C 8/11 ? cfi id string table, hex offset 13h: changed address 13 hex code to 00; changed ad- dress 14 hex code to 02. ? table: dc voltage characteristics and operating conditions: changed v il max to 0.45; changed v ih min to v ccq - 0.45. rev. d C 5/11 ? revised for reuse. rev. c C 2/11 ? added aad-mux description. rev. b C 12/10 ? made miscellaneous text edits and formatting improvements. rev. a C 12/10 ? initial release. 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 www.micron.com/productsupport customer comment line: 800-932-4992 micron and the micron logo are trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. 128mb, 256mb, 512mb, 1gb strataflash memory revision history pdf: 09005aef8448483a 128_256_512_65nm_g18.pdf - rev. f 8/11 en 118 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. |
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